Datasheet MC14511BCP, MC14511BD, MC14511BDW, MC14511BCL Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

361

MC14511B

 


The MC14511B BCD–to–seven s egment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven
segment decoder, and an output drive capability. Lamp test (LT

), blanking

(BI

), and latch enable (LE) inputs are used to test the display, to turn–off or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. It can be used with seven–segment light–emitting diodes
(LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts
either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.

• Low Logic Circuit Power Dissipation

• High–Current Sourcing Outputs (Up to 25 mA)

• Latch Storage of Code

• Blanking Input

• Lamp Test Provision

• Readout Blanking on all Illegal Input Combinations

• Lamp Intensity Modulation Capability

• Time Share (Multiplexing) Facility

• Supply Voltage Range = 3.0 V to 18 V

• Capable of Driving Two Low–power TTL Loads, One Low–power

Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range

• Chip Complexity: 216 FETs or 54 Equivalent Gates

• Triple Diode Protection on all Inputs

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Rating

Symbol Value Unit

DC Supply Voltage V

DD

– 0.5 to + 18 V

Input Voltage, All Inputs V

in

– 0.5 to VDD +0.5 V
DC Current Drain per Input Pin I 10 mA
Operating Temperature Range T

A

– 55 to + 125

_

C

Power Dissipation per Package† P

D

500 mW

Storage Temperature Range T

stg

– 65 to + 150

_

C

Maximum Output Drive Current

(Source) per Output

I

OHmax

25 mA

Maximum Continuous Output Power

(Source) per Output ‡

P

OHmax

50 mW

‡P

OHmax

= IOH (VDD – VOH)
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC
CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

DW SUFFIX

SOIC

CASE 751G

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

b

a

g

f

V

DD

e

d

c

BI

LT

C

B

V

SS

A

D

LE

0 1 2 3 4 5 6 7 8 9

DISPLAY

a

b

c

d

e

f g

ā

Depends upon the BCD code previously applied when LE = 0

TRUTH TABLE

LE BI LT D C B A a b c d e f g Display

X = Don’t Care
*

Inputs Outputs

X X 0 X X X X 1 1 1 1 1 1 1 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
0 1 1 0 0 0 0 1 1 1 1 1 1 0 0

0 1 1 0 0 0 1 0 1 1 0 0 0 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1 2
0 1 1 0 0 1 1 1 1 1 1 0 0 1 3

0 1 1 0 1 0 0 0 1 1 0 0 1 1 4
0 1 1 0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 1 0 0 0 1 1 1 1 1 6
0 1 1 0 1 1 1 1 1 1 0 0 0 0 7

0 1 1 1 0 0 0 1 1 1 1 1 1 1 8
0 1 1 1 0 0 1 1 1 1 0 0 1 1 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank

0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank

1 1 1 X X X X * *

MOTOROLA CMOS LOGIC DATAMC14511B

362

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic

Symbol

V

DD

Vdc

Min Max Min Typ # Max Min Max

Unit

“0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.1

9.1

14.1

—
—
—

4.1

9.1

14.1

4.57

9.58

14.59

—
—
—

4.1

9.1

14.1

—
—
—

Vdc

“0” Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level
(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

5.0 4.1
—

3.9
—

3.4
—

—
—
—
—
—
—

4.1
—

3.9
—

3.4
—

4.57

4.24

4.12

3.94

3.70

3.54

—
—
—
—
—
—

4.1
—

3.5
—

3.0
—

—
—
—
—
—
—

Vdc

10 9.1

—

9.0
—

8.6
—

—
—
—
—
—
—

9.1
—

9.0
—

8.6
—

9.58

9.26

9.17

9.04

8.90

8.70

—
—
—
—
—
—

9.1
—

8.6
—

8.2
—

—
—
—
—
—
—

Vdc

15 14.1

—
14
—

13.6
—

—
—
—
—
—
—

14.1
—
14
—

13.6
—

14.59

14.27

14.18

14.07

13.95

13.70

—
—
—
—
—
—

14.1
—

13.6
—

13.2
—

—
—
—
—
—
—

Vdc

Output Drive Current

(VOL = 0.4 V) Sink
(VOL = 0.5 V)
(VOL = 1.5 V)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) Vin = 0 or VDD,
I

out

= 0 µA

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

I

T

5.0
10
15

IT = (1.9 µA/kHz) f + I

DD

IT = (3.8 µA/kHz) f + I

DD

IT = (5.7 µA/kHz) f + I

DD

µAdc

#Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level =

1.0 Vdc min @ VDD = 5.0 Vdc

2.0 Vdc min @ VDD = 10 Vdc

2.5 Vdc min @ VDD = 15 Vdc
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

Output Voltage

Input Voltage #

Output Drive Voltage

(IOH = 0 mA) Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

V

OH

MOTOROLA CMOS LOGIC DATA

363

MC14511B

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

Symbol

V

DD

Vdc

Min Typ Max Unit

Output Rise Time

t

TLH

= (0.40 ns/pF) CL + 20 ns

t

TLH

= (0.25 ns/pF) CL + 17.5 ns

t

TLH

= (0.20 ns/pF) CL + 15 ns

t

TLH

5.0
10
15

—
—
—

40
30
25

80
60
50

ns

Output Fall Time

t

THL

= (1.5 ns/pF) CL + 50 ns

t

THL

= (0.75 ns/pF) CL + 37.5 ns

t

THL

= (0.55 ns/pF) CL + 37.5 ns

t

THL

5.0
10
15

—
—
—

125

75
65

250
150
130

ns

t

PLH

5.0
10
15

—
—
—

640
250
175

1280

500
350

t

PHL

5.0
10
15

—
—
—

720
290
200

1440

580
400

t

PLH

5.0

I0

15

—
—
—

600
200
150

750
300
220

t

PHL

5.0
10
15

—
—
—

485
200
160

970
400
320

t

PLH

5.0
10
15

—
—
—

313
125

90

625
250
180

t

PHL

5.0
10
15

—
—
—

313
125

90

625
250
180

Setup Time t

su

5.0
10
15

100

40
30

—
—
—

—
—
—

ns

Hold Time t

h

5.0
10
15

60
40
30

—
—
—

—
—
—

ns

Latch Enable Pulse Width t

WL

5.0
10
15

520
220
130

260
110

65

—
—
—

ns

*The formulas given are for the typical characteristics only.

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how­ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and V

out

are not constrained to the range VSS ≤ (Vin or

V

out

) ≤ VDD.

Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

Data Propagation Delay Time

t

= (0.40 ns/pF) CL + 620 ns

PLH

t

= (0.25 ns/pF) CL + 237.5 ns

PLH

t

= (0.20 ns/pF) CL + 165 ns

PLH

t

= (1.3 ns/pF) CL + 655 ns

PHL

t

= (0.60 ns/pF) CL + 260 ns

PHL

t

= (0.35 ns/pF) CL + 182.5 ns

PHL

Blank Propagation Delay Time

t

= (0.30 ns/pF) CL + 585 ns

PLH

t

= (0.25 ns/pF) CL + 187.5 ns

PLH

t

= (0.15 ns/pF) CL + 142.5 ns

PLH

t

= (0.85 ns/pF) CL + 442.5 ns

PHL

t

= (0.45 ns/pF) CL + 177.5 ns

PHL

t

= (0.35 ns/pF) CL + 142.5 ns

PHL

Lamp Test Propagation Delay Time

t

= (0.45 ns/pF) CL + 290.5 ns

PLH

t

= (0.25 ns/pF) CL + 112.5 ns

PLH

t

= (0.20 ns/pF) CL + 80 ns

PLH

t

= (1.3 ns/pF) CL + 248 ns

PHL

t

= (0.45 ns/pF) CL + 102.5 ns

PHL

t

= (0.35 ns/pF) CL + 72.5 ns

PHL

ns

ns

ns

MOTOROLA CMOS LOGIC DATAMC14511B

364

Figure 1. Dynamic Power Dissipation Signal Waveforms

Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.

20 ns 20 ns

V

DD

V

SS

V

OH

V

OL

90%

50%

10%

50%

A, B, AND C

ANY OUTPUT

50% DUTY CYCLE

1

2f

Figure 2. Dynamic Signal Waveforms

20 ns 20 ns

V

DD

90%

INPUT C

(a) Inputs D and LE low, and Inputs A, B, BI and LT high.

V

SS

V

OH

V

OL

50%
10%

OUTPUT g

t

PLH

t

PHL

90%

10%

50%

t

TLH

t

THL

(b) Input D low, Inputs A, B, BI and LT high.

20 ns

10%

90%

50%

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

t

h

t

su

50%

INPUT C

OUTPUT g

LE

(c) Data DCBA strobed into latches.

20 ns

20 ns

V

DD

V

SS

LE

90%

50%

10%

t

WL

MOTOROLA CMOS LOGIC DATA

365

MC14511B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

COMMON

CATHODE LED

≈

1.7 V

V

DD

V

SS

V

DD

COMMON

ANODE LED

V

SS

≈

1.7 V

LIGHT EMITTING DIODE (LED) READOUT

INCANDESCENT READOUT FLUORESCENT READOUT

GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT

V

DD

V

DD

**

V

SS

V

DD

V

SS

FILAMENT
SUPPLY

DIRECT
(LOW BRIGHTNESS)

VSS OR APPROPRIATE
VOLTAGE BELOW VSS.

(CAUTION: Maximum working voltage = 18.0 V)

V

DD

APPROPRIATE

VOLTAGE

V

SS

V

SS

V

DD

EXCITATION

(SQUARE WAVE,

VSS TO VDD)

1/4 OF MC14070B

**A filament pre–warm resistor is recommended to reduce filament

thermal shock and increase the effective cold resistance of the

filament.

Direct dc drive of LCD’s not recommended for life of
LCD readouts.

MOTOROLA CMOS LOGIC DATAMC14511B

366

LOGIC DIAGRAM

LE 5

D 6

C 2

B 1

A 7

VDD = PIN 16

VSS = PIN 8

BI

4

LT 3

14 g

15 f

9 e

10 d

11 c

12 b

13 a

MOTOROLA CMOS LOGIC DATA

367

MC14511B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53

F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74
M 0 10 0 10

S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65

G 0.100 BSC 2.54 BSC

H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC

M 0 15 0 15

N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATAMC14511B

368

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

_ _ _ _

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

M

B

M

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

–A–

–B– P8X

G14X

D16X

SEATING
PLANE

–T–

S

A

M

0.010 (0.25) B

S

T

16 9

81

F

J

R

X 45

_

_ _ _ _

M

C

K

MOTOROLA CMOS LOGIC DATA

369

MC14511B

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rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer .

MC14511B/D

*MC14511B/D*

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