Datasheet MC14511B Datasheet (ON Semiconductor)

MC14511B

BCD-To-Seven Segment
Latch/Decoder/Driver

The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output d rivers in a s ingle m onolithic s tructure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and an output drive capability. Lamp
test (LT

), blanking (BI), and latch enable ( LE) i nputs a re us ed t o t est t he
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven–segment
light–emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.

• Low Logic Circuit Power Dissipation

• High–Current Sourcing Outputs (Up to 25 mA)

• Latch Storage of Code

• Blanking Input

• Lamp Test Provision

• Readout Blanking on all Illegal Input Combinations

• Lamp Intensity Modulation Capability

• Time Share (Multiplexing) Facility

• Supply Voltage Range = 3.0 V to 18 V

• Capable of Driving Two Low–power TTL Loads, One Low–power

Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range

• Chip Complexity: 216 FETs or 54 Equivalent Gates

• Triple Diode Protection on all Inputs

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

DD

V

P

T

T

stg

I

OHmax

P

OHmax

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

4. P

OHmax

DC Supply Voltage Range –0.5 to +18.0 V
Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V

in

I DC Current Drain per Input Pin 10 mA

Power Dissipation,

D

A

per Package (Note 3)
Operating Temperature Range –55 to +125 °C
Storage Temperature Range –65 to +150 °C
Maximum Output Drive Current

(Source) per Output
Maximum Continuous Output

Power (Source) per Output

(Note 4)

= IOH (VDD – VOH)

) (Note 2)

SS

500 mW

25 mA

50 mA

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

SOIC–16
DW SUFFIX
CASE 751G

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

MC14511BCP

AWLYYWW

1

16

14511B

AWLYWW

1
16

14511B

AWLYYWW

1

16

MC14511B

ALYW

1

ORDERING INFORMATION

Device Package Shipping

MC14511BCP PDIP–16 2000/Box
MC14511BD SOIC–16 48/Rail
MC14511BDW SOIC–16 47/Rail
MC14511BDWR2 SOIC–16 1000/Tape & Reel
MC14511BF SOEIAJ–16 See Note 1
MC14511BFEL SOEIAJ–16 See Note 1

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2002

February, 2002 – Rev. 5

1 Publication Order Number:

MC14511B/D

MC14511B

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it i s advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages
to this high–impedance circuit. A destructive high current mode may occur if Vin and V
V

 (Vin or V

SS

)  VDD.

out

Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted
to V

and are at a logical 1 (See Maximum Ratings).

SS

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

PIN ASSIGNMENT

V

16

DD

15

f

fg

e

d

a

b

c

g

14

a

13

b

125

11

c

10

d

9

e

LE

V

B

C

LT

BI

D

A

SS

1

2

3

4

6

7

8

DISPLAY

are not constrained to the range

out

0123456789

TRUTH TABLE

Inputs Outputs

LE BI LT D C B A a b c d e f g Display

XX0XXXX1111111 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank

01100001111110 0
01100010110000 1
01100101111001 2
01100111111001 3

01101000110011 4
01101011011011 5
01101100011111 6
01101111110000 7

01110001111111 8
01110011110011 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank

0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank

111XXXX * *

X = Don’t Care
*Depends upon the BCD code previously applied when LE = 0

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2

MC14511B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

– 55C 25C 125C

V

DD

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

V

OL

Vdc

5.0
10
15

V

= 0 or V

in

DD

Input Voltage # “0” Level

“1” Level

(V

= 3.8 or 0.5 Vdc)

O

= 8.8 or 1.0 Vdc)

(V

O

(V

= 13.8 or 1.5 Vdc)

O

“1” Level

= 0.5 or 3.8 Vdc)

(V

O

(V

= 1.0 or 8.8 Vdc)

O

(V

= 1.5 or 13.8 Vdc)

O

Output Drive Voltage

= 0 mA) Source

(I

OH

(I

= 5.0 mA)

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

(I

= 20 mA)

OH

(I

= 25 mA)

OH

(IOH = 0 mA)
(I

= 5.0 mA)

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

= 20 mA)

(I

OH

(I

= 25 mA)

OH

(IOH = 0 mA)
(I

= 5.0 mA)

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

(I

= 20 mA)

OH

(I

= 25 mA)

OH

Output Drive Current

(V

= 0.4 V) Sink

OL

= 0.5 V)

(V

OL

(V

= 1.5 V)

OL

Input Current I
Input Capacitance C
Quiescent Current

(Per Package) V

= 0 µA

I

out

= 0 or VDD,

in

Total Supply Current (Notes 6 & 7)

(Dynamic plus Quiescent,
Per Package)
(C

= 50 pF on all outputs, all

L

V

OH

V

IL

V

IH

V

OH

I

OL

in

in

I

DD

I

T

5.0
10
15

5.0
10
15

5.0
10
15

5.0 4.1

10 9.1

15 14.1

5.0
10
15

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
— — — — 5.0 7.5 — — pF

5.0
10
15

5.0
10
15

buffers switching)

5. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =

1.0 Vdc min @ VDD = 5.0 Vdc

2.0 Vdc min @ V

2.5 Vdc min @ V

6. The formulas given are for the typical characteristics only at 25C.

= 10 Vdc

DD

= 15 Vdc

DD

7. To calculate total supply current at loads other than 50 pF:

) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf

I

T(CL

where: I

is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

T

Min Max Min

—
—
—

4.1

9.1

14.1

—
—
—

3.5

7.0
11

—

3.9
—

3.4
—

—

9.0
—

8.6
—

—
14
—

13.6
—

0.64

1.6

4.2

—
—
—

SS

)

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—

5.0
10
20

Typ

(Note 5)

—
—
—

4.1

9.1

14.1

—
—
—

3.5

7.0
11

4.1
—

3.9
—

3.4
—

9.1
—

9.0
—

8.6
—

14.1
—
14
—

13.6
—

0.51

1.3

3.4

—
—
—

0
0
0

4.57

9.58

14.59

2.25

4.50

6.75

2.75

5.50

8.25

4.57

4.24

4.12

3.94

3.70

3.54

9.58

9.26

9.17

9.04

8.90

8.70

14.59

14.27

14.18

14.07

13.95

13.70

0.88

2.25

8.8

0.005

0.010

0.015

IT = (1.9 µA/kHz) f + I
IT = (3.8 µA/kHz) f + I
IT = (5.7 µA/kHz) f + I

Max Min Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—

5.0
10
20

DD
DD
DD

—
—
—

4.1

9.1

14.1

—
—
—

3.5

7.0
11

4.1
—

3.5
—

3.0
—

9.1
—

8.6
—

8.2
—

14.1
—

13.6
—

13.2
—

0.36

0.9

2.4

—
—
—

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—

150
300
600

Unit

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

mAdc

µAdc

µAdc

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3

MC14511B

SWITCHING CHARACTERISTICS (Note 8) (C

= 50 pF, T

L

Characteristic

Output Rise Time

t

= (0.40 ns/pF) CL + 20 ns

TLH

= (0.25 ns/pF) CL + 17.5 ns

t

TLH

t

= (0.20 ns/pF) CL + 15 ns

TLH

Output Fall Time

t

= (1.5 ns/pF) CL + 50 ns

THL

= (0.75 ns/pF) CL + 37.5 ns

t

THL

t

= (0.55 ns/pF) CL + 37.5 ns

THL

Data Propagation Delay Time

t

= (0.40 ns/pF) CL + 620 ns

PLH

= (0.25 ns/pF) CL + 237.5 ns

t

PLH

t

= (0.20 ns/pF) CL + 165 ns

PLH

t

= (1.3 ns/pF) CL + 655 ns

PHL

= (0.60 ns/pF) CL + 260 ns

t

PHL

t

= (0.35 ns/pF) CL + 182.5 ns

PHL

Blank Propagation Delay Time

t

= (0.30 ns/pF) CL + 585 ns

PLH

t

= (0.25 ns/pF) CL + 187.5 ns

PLH

t

= (0.15 ns/pF) CL + 142.5 ns

PLH

t

= (0.85 ns/pF) CL + 442.5 ns

PHL

= (0.45 ns/pF) CL + 177.5 ns

t

PHL

t

= (0.35 ns/pF) CL + 142.5 ns

PHL

Lamp Test Propagation Delay Time

t

= (0.45 ns/pF) CL + 290.5 ns

PLH

t

= (0.25 ns/pF) CL + 112.5 ns

PLH

t

= (0.20 ns/pF) CL + 80 ns

PLH

t

= (1.3 ns/pF) CL + 248 ns

PHL

= (0.45 ns/pF) CL + 102.5 ns

t

PHL

t

= (0.35 ns/pF) CL + 72.5 ns

PHL

Setup Time t

Hold Time t

Latch Enable Pulse Width t

8. The formulas given are for the typical characteristics only.

= 25C)

A

Symbol

t

TLH

t

THL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

su

h

WL

V

DD

Vdc

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0

I0

15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

Min Typ Max Unit

ns
—
—
—

40
30
25

80
60
50

ns
—
—
—

125

75
65

250
150
130

ns
—
—
—

—
—
—

640
250
175

720
290
200

1280

500
350

1440

580
400

ns
—
—
—

—
—
—

600
200
150

485
200
160

750
300
220

970
400
320

ns
—
—
—

—
—
—

100

40
30

60
40
30

520
220
130

313
125

90

313
125

90
—

—
—

—
—
—

260
110

65

625
250
180

625
250
180

—
—
—

—
—
—

—
—
—

ns

ns

ns

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4

MC14511B

Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C

20 ns 20 ns

A, B, AND C

90%

1

50%

10%

2f

50% DUTY CYCLE

ANY OUTPUT

50%

Figure 1. Dynamic Power Dissipation Signal Waveforms

loads.

L

V

DD

V

SS

V

OH

V

OL

20 ns 20 ns

V

INPUT C

OUTPUT g

t

PLH

90%
50%
10%

t

PHL

50%

90%

10%

t

TLH

DD

V

SS

V

OH

V

OL

t

THL

(a) Inputs D and LE low, and Inputs A, B, BI and LT high.

LE

INPUT C

OUTPUT g

50%

20 ns

t

su

10%

50%

90%

t

h

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

(b) Input D low, Inputs A, B, BI and LT high.

20 ns

90%

LE

50%

10%

t

WL

(c) Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

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5

20 ns

V

DD

V

SS

MC14511B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

V

DD

COMMON

CATHODE LED

≈ 1.7 V

V

SS

INCANDESCENT READOUT FLUORESCENT READOUT

V

DD

V

DD

V

DD

COMMON

ANODE LED

V

SS

V

DD

≈ 1.7 V

**

DIRECT
(LOW BRIGHTNESS)

FILAMENT
SUPPLY

V

SS

V

SS

V

OR APPROPRIATE

SS

VOLTAGE BELOW V

(CAUTION: Maximum working voltage = 18.0 V)

GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT

APPROPRIATE

V

DD

VOLTAGE

V

DD

1/4 OF MC14070B

EXCITATION

(SQUARE WAVE,

TO VDD)

V

SS

.

SS

V

SS

**A filament pre–warm resistor is recommended to reduce filament

thermal shock and increase the effective cold resistance of the
filament.

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V

SS

Direct dc drive of LCD’s not recommended for life of
LCD readouts.

6

A7

MC14511B

4

BI

13a

12b

11c

B1

C2

D6

LE5

= PIN 16

V

DD

V

= PIN 8

SS

Figure 3. Logic Diagram

10d

9e

15f

14g

LT3

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7

MC14511B

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

–A–

916

B

18

F

C

S

SEATING

–T–

PLANE

H

G

D

16 PL

0.25 (0.010) T

K

M

A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

J

M

M

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53

F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



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8

MC14511B

PACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–T–

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

M

S

X 45

R



F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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9

MC14511B

PACKAGE DIMENSIONS

SOIC–16

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–03

ISSUE B

16 9

M

B

H8X

M

0.25

0.25 B

14X

D

B16X

M

S

A

T

e

A



NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

E



h X 45

81

B

S

A

L

A1

SEATING
PLANE

T

C

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

 0 7



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10

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC14511B

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

Q

M



L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED

1

c

AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

--- 2.05 --- 0.081

A

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L
L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

--- 0.78 --- 0.031

Z

INCHES

10



10

0





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MC14511B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

http://onsemi.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC14511B/D

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