Page 1
MOTOROLA CMOS LOGIC DATA
351
MC14510B
The MC14510B synchronous up/down BCD counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure. The counter consists of type D flip–flop stages with a gating
structure to provide type T flip–flop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. T he direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out
to the
Carry In
of the next stage while clocking e ach counter i n parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the
Reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital a nd digital–to–analog conversions, and (3) M agnitude and s ign
generation.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
• Asynchronous Preset Enable Operation
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Carry In Up/Down
Preset
Enable
Reset Clock Action
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out
signal is normally high, and is low only
when Q1 and Q4 are high and Carry In
is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
BLOCK DIAGRAM
1
5
9
10
15
4
12
13
3
6
11
14
2
7
PE
CARRY IN
R
UP/DOWN
CLOCK
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY
OUT
VDD = PIN 16
VSS = PIN 8
Page 2
MOTOROLA CMOS LOGIC DATAMC14510B
352
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (0.58 µA/kHz) f + I
DD
IT = (1.20 µA/kHz) f + I
DD
IT = (1.70 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
P2
P3
Q3
C
V
DD
R
U/D
Q2
P1
P4
Q4
PE
V
SS
CARRY OUT
Q1
CARRY IN
Page 3
MOTOROLA CMOS LOGIC DATA
353
MC14510B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C, See Figure 2)
All Types
Characteristic
Symbol
V
DD
Min Typ # Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
315
130
100
630
260
200
ns
Clock to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
315
130
100
630
260
200
ns
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
Carry In
to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 47 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 35 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
180
80
60
360
160
120
ns
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
Carry In
to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 47 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 35 ns
Preset or Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
315
130
100
630
260
200
ns
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
Carry In
to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 47 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 35 ns
Preset or Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 192 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 125 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
550
225
150
1100
450
300
ns
Reset Pulse Width t
w(H)
5.0
10
15
360
210
160
180
105
80
—
—
—
ns
Clock Pulse Width t
w(H)
5.0
10
15
350
170
140
200
100
75
—
—
—
ns
Clock Pulse Frequency f
cl
5.0
10
15
—
—
—
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time
The Preset or Reset Signal must be low prior to a
positive–going transition of the clock.
t
rem
5.0
10
15
650
230
180
325
115
90
—
—
—
ns
Clock Rise and Fall Time t
TLH
,
t
THL
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
Setup Time
Carry In
to Clock
t
su
5.0
10
15
260
120
100
130
60
50
—
—
—
ns
Hold Time
Clock to Carry In
t
h
5.0
10
15
0
10
10
– 50
– 15
– 5
—
—
—
ns
Setup Time
Up/Down to Clock
t
su
5.0
10
15
500
200
175
250
100
75
—
—
—
ns
Hold Time
Clock to Up/Down
t
h
5.0
10
15
– 70
– 30
– 20
– 140
– 80
– 50
—
—
—
ns
Setup Time
Pn to PE
t
su
5.0
10
15
– 50
– 30
– 25
– 100
– 65
– 55
—
—
—
ns
Hold Time
PE to Pn
t
h
5.0
10
15
480
410
410
240
205
205
—
—
—
ns
Preset Enable Pulse Width t
WH
5.0
10
15
200
100
80
100
50
40
—
—
—
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 4
MOTOROLA CMOS LOGIC DATAMC14510B
354
Figure 1. Power Dissipation Test Circuit and Waveform
Figure 2. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
0.01
µ
F
CERAMIC
V
DD
I
D
500 pF
PE
CARRY IN
R
UP/DOWN
CLOCK
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY
OUT
C
L
C
L
C
L
C
L
C
L
20 ns 20 ns
V
DD
V
SS
90%
50%
10%
CLOCK
VARIABLE
WIDTH
PROGRAMMABLE
PULSE
GENERATOR
V
DD
C
L
C
L
C
L
C
L
C
L
V
SS
PE
CARRY IN
R
UP/DOWN
CLOCK
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY
OUT
t
su
t
rem
50%
50%
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
SS
V
DD
1
fcl
t
w(H)
t
w(H)
t
TLH
t
PLH
t
PHL
t
PLH
t
THL
90%
10%
CARRY OUT
ONLY
t
w(H)
t
rem
20 ns
90%
10%
CARRY IN
OR
UP/DOWN
CLOCK
PRESET ENABLE
Q1 OR CARRY OUT
RESET
Page 5
MOTOROLA CMOS LOGIC DATA
355
MC14510B
LOGIC DIAGRAM
RESET
PRESET ENABLE
CLOCK
CARRY OUT
CARRY IN
UP/DOWN
P14Q1
6
P212Q2
11
P313Q3
14
P43Q4
2
P P P P
PE
D
C
PE
D
C
PE
D
C
PE
D
C
Q
Q
Q
Q
Q
Q
Q
Q
STATE DIAGRAM FOR UP COUNTING STATE DIAGRAM FOR DOWN COUNTING
15
14
13
12 11 10 9 8
7
6
5
43210 43210
15
14
13
12 11 10 9 8
7
6
5
Page 6
MOTOROLA CMOS LOGIC DATAMC14510B
356
PIN DESCRIPTIONS
INPUTS
P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In
, (Pin 5) — Active–low input used when cascading
stages. Usually connected to Carry Out
of the p revious
stage. While high, clock is inhibited.
Clock, ( Pin 1 5) — BCD data i s incremented o r decremented, depending on the direction of count, on the positive transition of this signal.
OUTPUTS
Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) — BCD
data is present on these outputs with Q1 corresponding to
the least significant bit.
Carry Out
, (Pin 7) — Used when cascading stages, this
pin is usually connected to Carry In
of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and will inhibit the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q outputs
to a low state. This pin is active high and will inhibit the clock
when high.
Up/Down, (Pin 10) — Controls the direction of count: high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, ( Pin 8) — This pin i s
usually connected to ground.
VDD, Positive Supply V oltage, (Pin 16) — This pin is con-
nected to a positive supply voltage ranging from 3.0 Vdc to
18.0 Vdc.
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) does not change while C
in
is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9
(count up mode), C
out
goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one
count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated.
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PE
C
in
CLOCK
U/D
R
PE
C
in
CLOCK
U/D
R
P1 P2 P3 P4
P1 P2 P3 P4
C
out
C
out
L.S.D.
MC14510B
M.S.D.
MC14510B
TERMINAL
COUNT
INDICATOR
0 = COUNT
PRESET
ENABLE
1 = PRESET
1 = UP
0 = DOWN
P1 P2 P3 P4 P5 P6 P7 P8
+V
DD
+V
DD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
RESISTORS = 10 k
Ω
CLOCK
+V
DD
RESET
OPEN = COUNT
Page 7
MOTOROLA CMOS LOGIC DATA
357
MC14510B
TIMING DIAGRAM FOR THE PRESETTABLE
CASCADED 8–BIT UP/DOWN COUNTER
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P8
P7
P6
P5
P4
P3
P2
P1
CARRY OUT
(MSD)
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CARRY OUT
(LSD)
RESET
COUNT MSD
COUNT LSD
6 6 6 7 7 7 7 7
7 7 6 6 6 6 9 9 9 9 9 0 0 0 0 00 0 0
7 8 9 0 1 2 3 2 1 0 9 8 7 6 6 6 7 8 9 0 1 2 1 00 1 0
PRESET ENABLE
DOWN
COUNT
UP COUNT DOWN COUNT UP COUNT UP COUNT
RESET
PRESET
ENABLE
Page 8
MOTOROLA CMOS LOGIC DATAMC14510B
358
Figure 4. Programmable Cascaded Frequency Divider
Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For
example, the maximum divide ratio of 99 may be obtained by applying a 1001 1001 to the preset inputs P0 to P7. For this divide
operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and
should be avoided.
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PE
C
in
CLOCK
U/D
P1 P2 P3
C
out
L.S.D.
MC14510B
P1 P2 P3
P4 P5 P6 P7
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
RESISTORS = 10 k
Ω
CLOCK (fin)
+V
DD
RESET
OPEN = COUNT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
M.S.D.
MC14510B
PE
C
in
CLOCK
U/D
R
R
BUFFER
f
out
P0
+V
DD
+V
DD
f
out
=
f
in
n
C
out
P4
P1 P2 P3 P4
Page 9
MOTOROLA CMOS LOGIC DATA
359
MC14510B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 10
MOTOROLA CMOS LOGIC DATAMC14510B
360
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14510B/D
*MC14510B/D*
◊
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