SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145053/D
CMOS
This ratiometric 10-bit ADC has a serial interface port to provide communi-
cation with MCUs and MPUs.
Either a 10- or 16-bit format can be used
16-bit format can be one continuous 16-bit stream or two intermittent 8-bit
streams. The converter operates from a single power supply with no external
trimming required. Reference voltages down to 4.0 V are accommodated.
The MC145053 has an internal clock oscillator to operate the dynamic A/D
conversion sequence and an end-of-conversion (EOC) output.
• 5 Analog Input Channels with Internal Sample-and-Hold
• Operating Temperature Range: – 40 to 125° C
• Successive Approximation Conversion Time: 44 µs Maximum
• Maximum Sample Rate: 20.4 ks/s
• Analog Input Range with 5-Volt Supply: 0 to 5 V
• Monotonic with No Missing Codes
• Direct Interface to Motorola SPI and National MICROWIRE Serial Data
Ports
• Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
• Low Power Consumption: 14 mW
• Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
• See Application Note AN1062 for Operation with QSPI
BLOCK DIAGRAM
V
ref
98
MUX OUT
10-BIT RC DAC
WITH SAMPLE AND HOLD
. The
V
AG
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOG
CASE 751A
ORDERING INFORMATION
MC145053P Plastic DIP
MC145053D SOG Package
PIN ASSIGNMENT
EOC
AN0
AN1
AN2
AN3
AN4
V
SS
1
2
3
4
6
7
14
13
12
11
105
V
DD
SCLK
D
in
D
out
CS
9
V
ref
V
8
AG
2
AN0
3
AN1
AN2
AN3
AN4
INTERNAL
TEST
VOLTAGES
MICROWIRE is a trademark of National Semiconductor Corp.
REV 2
1/99
MOTOROLA WIRELESS SEMICONDUCTOR
Motorola, Inc. 1998
SOLUTIONS DEVICE DA TA
AN5
AN6
AN7
D
in
D
out
CS
SCLK
EOC
4
5
6
12
11
10
13
ANALOG
MUX
1
MUX ADDRESS
REGISTER
DIGITAL CONTROL
LOGIC
SUCCESSIVE APPROXIMA TION
REGISTER
DATA REGISTER
PIN 14 = V
DD
PIN 7 = V
SS
AUTO-ZEROED
COMPARATOR
MC145053
1
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
V
V
V
I
IDD, ISSDC Supply Current, VDD and VSS Pins ± 50 mA
T
*Maximum Ratings are those values beyond which damage to the device may occur. Func-
tional operation should be restricted to the Operation Ranges below..
DC Supply Voltage (Referenced to VSS) – 0.5 to + 6.0 V
DD
DC Reference Voltage VAG to VDD + 0.1 V
ref
Analog Ground VSS – 0.1 to V
AG
V
DC Input Voltage, Any Analog or Digital
in
Input
DC Output Voltage VSS – 0.5 to
out
I
DC Input Current, per Pin ± 20 mA
in
DC Output Current, per Pin ± 25 mA
out
Storage Temperature – 65 to 150 °C
stg
T
Lead Temperature, 1 mm from Case for
L
10 Seconds
VSS – 0.5 to
VDD + 0.5
VDD + 0.5
260 °C
ref
V
V
V
OPERATION RANGES (Applicable to Guaranteed Limits)
Symbol
V
V
V
Vin, V
NOTE: Analog input voltages greater than V
DC Supply Voltage, Referenced to V
DD
DC Reference Voltage VAG + 4.0 to VDD + 0.1 V
ref
Analog Ground VSS – 0.1 to V
AG
V
Analog Input Voltage (See Note) VAG to V
AI
Digital Input Voltage, Output Voltage VSS to V
out
T
Ambient Operating Temperature – 40 to 125 °C
A
descriptions.
Parameter Value Unit
SS
convert to full scale. Input voltages less than VAG convert to zero. See V
ref
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
proper operation, Vin and V
constrained to the range VSS ≤ (Vin or V
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.
4.5 to 5.5 V
should be
out
– 4.0 V
ref
ref
DD
and VAG pin
ref
out
) ≤
V
V
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full T emperature and Voltage Ranges per Operation Ranges T able, unless otherwise indicated)
Guaranteed
Symbol
V
IH
V
IL
V
OH
V
OL
I
in
I
OZ
I
DD
I
ref
I
Al
Parameter Test Condition
Minimum High-Level Input Voltage
(Din, SCLK, CS
Maximum Low-Level Input Voltage
(Din, SCLK, CS
Minimum High-Level Output Voltage
(D
, EOC)
out
Minimum Low-Level Output Voltage
(D
, EOC)
out
Maximum Input Leakage Current
(Din, SCLK, CS
Maximum Three-State Leakage Current (D
Maximum Power Supply Current Vin = VSS or VDD, All Outputs Open 2.5 mA
Maximum Static Analog Reference Current (V
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0 – AN4)
)
)
I
= – 1.6 mA
out
I
= – 20 µA
out
I
= + 1.6 mA
out
I
= + 20 µA
out
)
) V
out
) V
ref
Vin = VSS or V
= VSS or V
out
= VDD, VAG = V
ref
VAl = VSS to V
DD
DD
SS
DD
Limit
VDD – 0.1
Unit
2.0 V
0.8 V
2.4
0.4
0.1
± 2.5 µA
± 10 µA
100 µA
± 1 µA
V
V
MC145053
2
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Characteristic
Resolution Number of bits resolved by the A/D converter 10 Bits
Maximum Nonlinearity Maximum difference between an ideal and an actual ADC transfer function ± 1 LSB
Maximum Zero Error Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
Maximum Full-Scale Error Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
Maximum Total Unadjusted Error Maximum sum of nonlinearity, zero error, and full-scale error ± 1 LSB
Maximum Quantization Error Uncertainty due to converter resolution ± 1/2 LSB
Absolute Accuracy Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
Maximum Conversion Time Total time to perform a single analog-to-digital conversion 44 µs
Data Transfer Time Total time to transfer digital serial data into and out of the device 10 to 16 SCLK
Sample Acquisition Time Analog input acquisition time window 6 SCLK
Minimum Total Cycle Time Total time to transfer serial data, sample the analog input, and perform the
conversion; SCLK = 2.1 MHz
Maximum Sample Rate Rate at which analog inputs may be sampled; SCLK = 2.1 MHz 20.4 ks/s
Definition and Test Conditions
Limit
± 1 LSB
± 1 LSB
± 1-1/2 LSB
49 µs
Unit
cycles
cycles
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
MC145053
3
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
1 f Clock Frequency, SCLK (10-bit xfer) Min
1 t
1 t
1, 7 t
1, 7 t
2, 7 t
2, 7 t
3 t
3 t
4, 7, 8 t
5 t
— t
— t
5 t
6, 8 t
1 tr, t
1, 4, 6 – 8 t
— C
— C
NOTES:
1. After the 10th SCLK falling edge (≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5 µs.
2. A CS
Symbol Parameter
Note: Refer to twH, twL below (10- to 16-bit xfer) Max)
wH
wL
, t
PLH
h
, t
PLZ
, t
PZL
su
h
d
su
CSd
CAs
h
PHL
, t
TLH
out
edge may be received immediately after an active transition on the EOC pin.
Minimum Clock High Time, SCLK 190 ns
Minimum Clock Low Time, SCLK 190 ns
Maximum Propagation Delay, SCLK to D
PHL
Minimum Hold Time, SCLK to D
Maximum Propagation Delay, CS to D
PHZ
Maximum Propagation Delay, CS to D
PZH
Minimum Setup Time, Din to SCLK 100 ns
Minimum Hold Time, SCLK to D
Maximum Delay Time, EOC to D
Minimum Setup Time, CS to SCLK 2.425 µs
Minimum Time Required Between 10th SCLK Falling Edge (≤ 0.8 V) and
CS
to Allow a Conversion
Maximum Delay Between 10th SCLK Falling Edge (≤ 2 V) and CS to
Abort a Conversion
Minimum Hold Time, Last SCLK to CS 0 ns
Maximum Propagation Delay, 10th SCLK to EOC 2.35 µs
Maximum Input Rise and Fall Times SCLK
f
Maximum Output Transition Time, Any Output 300 ns
THL
Maximum Input Capacitance AN0 – AN4
in
Maximum Three-State Output Capacitance D
out
in
out
High-Z 150 ns
out
Driven 2.3 µs
out
(MSB) 100 ns
out
(11- to 16-bit xfer) Min
Din, CS
SCLK, CS
, D
out
Guaranteed
Limit
0
Note 1
2.1
125 ns
10 ns
0 ns
Note 2
9 µs
1
10
55
in
15
15 pF
Unit
MHz
ms
µs
pF
MC145053
4
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
SWITCHING WAVEFORMS
SCLK
D
out
D
SCLK
in
t
f
2.0 V
t
h
t
wL
0.8 V
2.4 V
0.4 V
Figure 1.
VALID
2.0 V
0.8 V
t
su
1/f
t
PLH
t
TLH
, t
t
wH
PHL
, t
t
r
THL
0.8 V
2.0 V
PZL
2.0 V
90%
10%
t
PHZ
, t
PLZ
CS
D
out
0.8 V
2.4 V
0.4 V
t
PZH
, t
Figure 2.
t
TLH
EOC
0.4 V
t
h
D
out
NOTE: D
2.4 V
t
d
2.4 V
0.4 V
VALID MSB
is driven only when CS is active (low).
out
CS
SCLK
DEVICE
UNDER
TEST
0.8 V
D
Figure 3.
t
su
FIRST
CLOCK
Figure 5.
out
12 k 100 pF
TEST
POINT
LAST
CLOCK
V
DD
0.8 V0.8 V
2.18 k
2.0 V
t
h
SCLK
EOC
DEVICE
UNDER
TEST
10TH
CLOCK
EOC
Figure 4.
0.8 V
2.4 V
t
THL
Figure 6.
TEST
POINT
12 k 50 pF
t
0.4 V
PHL
V
DD
2.18 k
Figure 7. T est Circuit
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
Figure 8. T est Circuit
MC145053
5
PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUT
The various serial bit-stream formats for the MC145053
are illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADC accepts 16 clocks which makes it SPI (Serial
Peripheral Interface) compatible.
T able 1. Timing Diagram Selection
No. of Clocks in
Serial Transfer
10 Yes Don’t Care 9
10 No Don’t Care 10
11 to 16 Yes Shorter than Conversion 11
16 No Shorter than Conversion 12
11 to 16 Yes Longer than Conversion 13
16 No Longer than Conversion 14
CS
Active-Low Chip Select Input (Pin 10)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (D
inactive high, CS
and disables the data input (Din) and serial clock (SCLK)
pins. A high-to-low transition on CS
port and synchronizes it to the MPU data stream. CS
main active during the conversion cycle and can stay in the
active low state for multiple serial transfers or CS
active high after each transfer. If CS
tween transfers, the length of each transfer is limited to either
10 or 16 SCLK cycles. If CS
tween transfers, each transfer can be anywhere from 10 to
16 SCLK cycles long. See the SCLK pin description for a
more detailed discussion of these requirements.
Spurious chip selects caused by system noise are minimized by the internal circuitry. Any transitions on the CS
are recognized as valid only if the level is maintained for
about 2 µs after the transition.
If CS
is inactive high after the 10th SCLK cycle
and then goes active low before the A/D conversion is complete, the conversion is aborted and
the chip enters the initial state, ready for another
serial transfer/conversion sequence. At this point,
the output data register contains the result from
the conversion before the aborted conversion.
Note that the last step of the A/D conversion sequence is to update the output data register with
the result. Therefore, if CS
attempt to abort the conversion too close to the
end of the conversion sequence, the result register may be corrupted and the chip could be thrown
out of sync with the processor until CS
again (refer to the AC Electrical Characteristics in
the spec tables).
Using
CS
forces D
Serial Transfer
Interval
to the high-impedance state
out
out
Figure
No.
). While
resets the serial data
can re-
can be in-
is kept active low be-
is in the inactive high state be-
NOTE
goes active low in an
is toggled
pin
D
out
Serial Data Output of the A/D Conversion Result
(Pin 11)
This output is in the high-impedance state when CS
is in-
active high. When the chip recognizes a valid active low on
, D
CS
is taken out of the high-impedance state and is driv-
out
en with the MSB of the previous conversion result. (For the
first transfer after power-up, data on D
entire transfer.) The value on D
out
is undefined for the
out
changes to the second
most significant result bit upon the first falling edge of SCLK.
The remaining result bits are shifted out in order, with the
LSB appearing on D
upon the ninth falling edge of SCLK.
out
Note that the order of the transfer is MSB to LSB. Upon the
10th falling edge of SCLK, D
allowed by CS
) so that transfers of more than 10 SCLKs read
is immediately driven low (if
out
zeroes as the unused LSBs.
When CS
is held active low between transfers, D
out
is driven from a low level to the MSB of the conversion result for
three cases: Case 1 — upon the 16th SCLK falling edge if
the transfer is longer than the conversion time (Figure 14);
Case 2 — upon completion of a conversion for a 16-bit transfer interval shorter than the conversion (Figure 12); Case 3
— upon completion of a conversion for a 10-bit transfer (Figure 10).
D
in
Serial Data Input (Pin 12)
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be converted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on Din is ignored for the remainder of the
present serial transfer. See Table 2 in Applications In-
formation.
SCLK
Serial Data Clock (Pin 13)
This clock input drives the internal I/O state machine to
perform three major functions: (1) drives the data shift registers to simultaneously shift in the next mux address from the
Din pin and shift out the previous conversion result on the
D
pin, (2) begins sampling the analog voltage onto the RC
out
DAC as soon as the new mux address is available, and (3)
transfers control to the A/D conversion state machine after
the last bit of the previous conversion result has been shifted
out on the D
out
pin.
The serial data shift registers are completely static, allowing SCLK rates down to the dc. There are some cases, however, that require a minimum SCLK frequency as discussed
later in this section. At least ten SCLK cycles are required for
each simultaneous data transfer. If the 16-bit format is used,
SCLK can be one continuous 16-bit stream or two intermittent 8-bit streams. After the serial port has been initiated to
perform a serial transfer*, the new mux address is shifted in
*The serial port can be initiated in three ways: (1) a recognized CS
falling edge, (2) the end of an A/D conversion if the port is performing either a 10-bit or a 16-bit “shorter-than-conversion” transfer
with CS
active low between transfers, and (3) the 16th falling edge
of SCLK if the port is performing 16-bit “longer-than-conversion”
transfers with CS
active low between transfers.
MC145053
6
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
on the first four rising edges of SCLK, and the previous 10-bit
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK
(the fourth falling edge), the analog input voltage on the
selected mux input begins charging the RC DAC and continues to do so until the tenth falling edge of SCLK. After this
tenth SCLK edge, the analog input voltage is disabled from
the RC DAC and the RC DAC begins the “hold” portion of the
A/D conversion sequence. Also upon this tenth SCLK edge,
control of the internal circuitry is transferred to the internal
clock oscillator which drives the successive approximation
logic to complete the conversion. If 16 SCLK cycles are used
during each transfer, then there is a constraint on the minimum SCLK frequency. Specifically, there must be at least
one rising edge on SCLK before the A/D conversion is complete. If the SCLK frequency is too low and a rising edge
does not occur during the conversion, the chip is thrown out
of sync with the processor and CS
der to restore proper operation. If 10 SCLKs are used per
transfer, then there is no lower frequency limit on SCLK. Also
note that if the ADC is operated such that CS
between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10 SCLKs
are used. (If CS
number of SCLK cycles must be either 10 or 16.)
EOC
End-of-Conversion Output (Pin 1)
EOC goes low on the tenth falling edge of SCLK. A low-tohigh transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
stays active low for multiple transfers, the
needs to be toggled in or-
is inactive high
and leakage currents through the ESD protection diodes on
the selected channel occur. These leakage currents cause
an offset voltage to appear across any series source resistance on the selected channel. Therefore, any source resistance greater than 1 kΩ (Motorola test condition) may induce
errors in excess of guaranteed specifications.
There are three tests available that verify the functionality
of all the control logic as well as the successive approximation comparator. These tests are performed by addressing
$B, $C, or $D and they convert a voltage of (V
VAG, or V
ly by sampling V
the RC DAC during the sample phase. Addressing $B, $C, or
$D produces an output of $200 (half scale), $000, or $3FF
(full scale), respectively, if the converter is functioning properly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip) on
VDD, VSS, V
POWER AND REFERENCE PINS
VSS and V
Device Supply Pins (Pins 7 and 14)
VSS is normally connected to digital ground; VDD is connected to a positive digital supply voltage. Low frequency
(VDD – VSS) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges
Table for restrictions on V
VSS.) Excessive inductance in the VDD or VSS lines, as on
automatic test equipment, may cause A/D offsets > ± 1 LSB.
Use of a 0.1 µF bypass capacitor across these pins is recommended.
, respectively. The voltages are obtained internal-
ref
DD
or VAG onto the appropriate elements of
ref
, or VAG.
ref
and VAG relative to VDD and
ref
+ VAG)/2,
ref
ANALOG INPUTS AND TEST MODES
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3
by $3, and AN4 by $4. Table 2 shows the input format for a
16-bit stream. The mux features a break-before-make
switching structure to minimize noise injection into the analog inputs. The source resistance driving these inputs must
be v 1 kΩ.
During normal operation, leakage currents through the
analog mux from unselected channels to a selected channel
VAG and V
Analog Reference V oltage Pins (Pins 8 and 9)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input voltages ≥ V
≤ VAG produce an output of zero. CAUTION: The analog
input voltage must be ≥ VSS and ≤ VDD. The A/D conversion
result is ratiometric to V
noise-free as possible to avoid degradation of the A/D
conversion. Ideally , V
nected to the voltage supply driving the system’s transducers. Use of a 0.22 µF bypass capacitor across these pins is
strongly urged.
ref
produce a full scale output and input voltages
ref
– VAG. V
ref
and VAG should be single-point con-
ref
and VAG must be as
ref
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
MC145053
7
CS
D
out
SCLK
D
in
EOC
CS
D9 – MSB
MSB
D8 D7 D6 D5 D4 D3 D2 D1 D0 D9
12345678910 1
SAMPLE ANALOG INPUT
A3 A2 A1 A0
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
HIGH IMPEDANCE
A/D CONVERSION
INTERV AL
RE-INITIALIZEINITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS
MUST BE HIGH ON POWER UP
A3
D
SCLK
EOC
D9 – MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 D9
out
12345678910 1
SAMPLE ANALOG INPUT
D
in
INITIALIZE
A3 A2 A1 A0 A3
MSB
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTES:
1. D9, D8, D7, D6, D5, …, D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
LOW LEVEL
A/D CONVERSION
INTERV AL
MC145053
8
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
D9
HIGH
IMPEDANCE
LOW
LEVEL
1
D9
1
A3
RE-INITIALIZE
INTERV AL
A/D CONVERSION
LOW LEVEL
12 13 14 15
A3A3 A2 A1 A0
A/D CONVERSION INTERV AL
CS
D8 D7 D6 D5 D4 D3 D2 D1 D0
D9 – MSB
out
D
SAMPLE ANALOG INPUT
123456789101116
SCLK
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A3 A2 A1 A0
Figure 11. T iming for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
in
D
EOC
INITIALIZE
MUST BE HIGH ON POWER UP
D9 – MSB D8 D7 D6 D5 D4 D3 D2 D1 D0
CS
D
out
SAMPLE ANALOG INPUT
1234567891011 16
SCLK
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
MSB
in
D
EOC
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
INITIALIZE
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
NOTES:
*This figure illustrates the behavior of the MC145051. The MC145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
MC145053
9
D9
HIGH
IMPEDANCE
LOW
LEVEL
1
D9
1
2
NOTE
A3
RE-INITIALIZE
A/D
INTERVAL
CONVERSION
LOW LEVEL
A3
NOTE 2
CS
D8 D7 D6 D5 D4 D3 D2 D1 D0
D9 – MSB
out
D
SAMPLE ANALOG INPUT
123456789101116
SCLK
12 13 14 15
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A3 A2 A1 A0
Figure 13. Timing for 1 1- to 16-Clock Transfer Using CS* (Serial Transfer Interval Longer Than Conversion)
in
D
EOC
INITIALIZE
MUST BE HIGH ON POWER UP
D8 D7 D6 D5 D4 D3 D2 D1 D0
D9 – MSB
SAMPLE ANALOG INPUT
1234567891011 16
A3 A2 A1 A0
MSB
INTERV AL
A/D CONVERSION
SHIFT IN NEW MUX ADDRESS,
Figure 14. Timing for 16-Clock T ransfer Not Using CS* (Serial Transfer Interval Longer Than Conversion)
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
MC145053
10
CS
D
out
SCLK
in
D
EOC
INITIALIZE
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
NOTES:
1. This figure illustrates the behavior of the MC145051. The MC145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
2. The 11th SCLK rising edge must occur before the conversion is complete. Otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer.
*NOTES:
APPLICATIONS INFORMATION
DESCRIPTION
This example application of the MC145053 ADC interfaces
four analog signals to a microprocessor.
Figure 15 illustrates how the MC145053 is used as a costeffective means to simplify this type of circuit design. Utilizing
one ADC, four analog inputs are interfaced to a CMOS or
NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor’s
MICROWIRE serial port may also be used. Full duplex
operation optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
Motorola’s MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may
be used if power consumption is not critical. A VDD or V
0.1 µF bypass capacitor should be closely mounted to the
ADC.
The MC145053 has the end-of-conversion (EOC) signal at
output pin 1 to define when data is ready.
ANALOG DESIGN CONSIDERATIONS
Analog signal sources with output impedances of less than
1 kΩ may be directly interfaced to the ADC, eliminating the
need for buffer amplifiers. Separate lines connect the V
and VAG pins on the ADC with the controllers to provide
isolation from system noise.
Although not indicated in Figure 15, the V
output lines may need to be shielded, depending on their
length and electrical environment. This should be verified
during prototyping with an oscilloscope. If shielding is
required, a twisted pair or foil-shielded wire (not coax) is
appropriate for this low frequency application. One wire of
the pair or the shield must be VAG.
and sensor
ref
SS
ref
A reference circuit voltage of 5 volts is used for the application shown in Figure 15. However, the reference circuitry
may be simplified by tying VAG to system ground and V
the system’s positive supply. (See Figure 16.)
A bypass capacitor of approximately 0.22 µF across the
V
and VAG pins is recommended. These pins are adjacent
ref
on the ADC package which facilitates mounting the capacitor
very close to the ADC.
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straightforward. The
four analog inputs, AN0 through AN3, are scanned by reading the analog value of the previously addressed channel
into the MCU and sending the address of the next channel to
be read to the ADC, simultaneously .
The designer utilizing the MC145053 has the end-of-conversion signal (at pin 1) to define the conversion interval.
EOC may be used to generate an interrupt, which is serviced
by reading the serial data from the ADC. The software flow
should then process and format the data.
When this ADC is used with a 16-bit (2-byte) transfer, there
are two types of offsets involved. In the first type of offset, the
channel information sent to the ADCs is offset by 12 bits.
That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don’t cares. This results in 3 don’t-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADC; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
result. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column
shows the result after the offset is removed by a microprocessor routine. If the 16-bit format is used, the ADC can
transfer one continuous 16-bit stream or two intermittent 8-bit
streams.
ref
to
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
MC145053
11
Table 2. Programmer’s Guide for 16-Bit Transfers:
Input Code
Table 3. Programmer’s Guide for 16-Bit Transfers:
Output Code
Input
Address
in Hex
$0XXX
$1XXX
$2XXX
$3XXX
$4XXX
$5XXX
$6XXX
$7XXX
$8XXX
$9XXX
$AXXX
$BXXX
$CXXX
$DXXX
$EXXX
$FXXX
Channel to be
Converted Next
AN0
AN1
AN2
AN3
AN4
None
None
None
None
None
None
AN5
AN6
AN7
None
None
Comment
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Half Scale Test: Output = $8000
Zero Test: Output = $0000
Full Scale Test: Output = $FFC0
Not Allowed
Not Allowed
0.22 µF
ANALOG
SENSORS,
ETC.
Conversion
Result Without
Offset Removed
V
ref
AN0
AN1
MC145053
ADC
AN2
AN3
$0000
$0040
$0080
$00C0
$0100
$0140
$0180
$01C0
$0200
$0240
$0280
$02C0
L
$FF40
$FF80
$FFC0
+ 5 V
V
DD
Conversion
Result With
Offset Removed
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$03FD
$03FE
$03FF
0.1
µ
F
CS
D
in
SCLK
D
out
EOC
Value
Zero
Zero + 1 LSB
Zero + 2 LSBs
Zero + 3 LSBs
Zero + 4 LSBs
Zero + 5 LSBs
Zero + 6 LSBs
Zero + 7 LSBs
Zero + 8 LSBs
Zero + 9 LSBs
Zero + 10 LSBs
L
Zero + 11 LSBs
L
Full Scale – 2 LSBs
Full Scale – 1 LSB
Full Scale
µ
P
SPI PORT
5 VOLT
REFERENCE
CIRCUIT
AN4
V
AG
Figure 15. Example Application
V
SS
MC145053
12
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
DIGITAL + V
Instruction
SPI
Device
ANALOG + V
DO NOT CONNECT
AT IC
V
ref
V
DD
5 V
SUPPLY
TO
SENSORS,
ETC.
ANALOG GND
DIGITAL GND
V
AG
MC145053
V
SS
DO NOT CONNECT
AT IC
0.1 µF0.22 µF
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola’s MCUs/MPUs.
Contact your Motorola representative if you need
Instruction
Set
M6805 2096
M68000 — — — MC68HC000
SPI = Serial Peripheral Interface.
SCI = Serial Communication Interface.
High Speed.
Low Power.
additional information.
Memory (Bytes)
ROM EEPROM
2096
4160
4160
8K
4160
8K
7700
—
—
—
—
—
—
—
—
—
4160
SPI
SCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
Device
Number
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HSC05C4
MC68HSC05C8
MC68HCL05C4
MC68HCL05C8
MC68HC05C8
MC68HC805C4
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
MC145053
13
P ACKAGE DIMENSIONS
14 8
B
17
A
F
C
N
SEATING
HG D
PLANE
K
PLASTIC DIP
P SUFFIX
CASE 646-06
L
J
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION
AT SEATING PLANE AT MAXIMUM MATERIAL
CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED
PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
MIN MINMAX MAX
DIM
A
B
C
D
F
G
H
J
K
L
M
N
0.715
0.240
0.145
0.015
0.040
0.100 BSC
0.052
0.008
0.115
0.300 BSC
°
0
0.015
0.770
0.260
0.185
0.021
0.070
0.095
0.015
0.135
10
0.039
°
18.16
6.10
3.69
0.38
1.02
2.54 BSC
1.32
0.20
2.92
7.62 BSC
0°
0.39
19.56
6.60
4.69
0.53
1.78
2.41
0.38
3.43
10
1.01
°
MC145053
14
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DA TA
SEATING
PLANE
SOG PACKAGE
D SUFFIX
CASE 751A-03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
-A-
814
-B- P 7 PL
M M
1
G
D 14 PL
0.25 (0.010)
7
M
K
T
C
S S
BA
R
X 45°
B0.25 (0.010)
F
M
J
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
A
8.55
B
3.80
C
1.35
D
0.35
F
0.40
1.27 BSC 0.050 BSC
G
J
0.19
K
0.10
M
0
°
P
5.80
R
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
°
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
°
°
0.244
0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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MOTOROLA WIRELESS SEMICONDUCTOR
◊
MC145053
MC145053/D
SOLUTIONS DEVICE DA TA
15
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