Datasheet MC14504BFL1, MC14504BFR1, MC14504BFR2, MC14504BF, MC14504BDR2 Datasheet (MOTOROLA)
...Page 1
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14504B/D
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non–inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels V
DD
and VCC. The
V
CC
level sets the input signal levels while VDD selects the output
voltage levels.
• UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
• Input Threshold Can Be Shifted for TTL Compatibility
• No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
• 3 to 18 Vdc Operation for V
DD
and V
CC
• Diode Protected Inputs to V
SS
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol Parameter Value Unit
V
CC
DC Supply Voltage Range –0.5 to +18.0 V
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
Input Voltage Range
(DC or Transient)
–0.5 to +18.0 V
V
out
Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and V
out
should be constrained
to the range V
SS
v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or VDD). Unused outputs must be left open.
http://onsemi.com
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14504BCP PDIP–16 2000/Box
MC14504BD SOIC–16 48/Rail
MC14504BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14504BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14504B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14504B
AWLYWW
MC14504BF SOEIAJ–16 See Note 1.
MC14504BFEL SOEIAJ–16 See Note 1.
MC14504BDT TSSOP–16 96/Rail
TSSOP–16
DT SUFFIX
CASE 948F
14
504B
ALYW
1
16
Page 2
MC14504B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
E
out
MODE
F
in
F
out
V
DD
D
in
D
out
E
in
B
out
A
in
A
out
V
CC
V
SS
C
in
C
out
B
in
LOGIC DIAGRAM
INPUT
V
DD
OUTPUT
LEVEL
SHIFTER
MODE
V
CC
TTL/CMOS
MODE SELECT
Mode Select
Input Logic
Levels
Output Logic
Levels
1 (VCC) TTL CMOS
0 (VSS) CMOS CMOS
1/6 of package shown.
Page 3
MC14504B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
CC
Vdc
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
ООООООООО
Î
Output Voltage “0” Level
V
in
= 0 V
“
”
ÎÎ
Î
V
OL
Î
Î
—
—
—
5.0
10
1 5
Î
Î
—
—
—
Î
Î
0.05
0.05
0.05
Î
Î
—
—
—
ÎÎ
Î
0
0
0
Î
Î
0.05
0.05
0.05
—
—
—
Î
Î
0.05
0.05
0.05
Î
Î
Vdc
ООООООООО
Î
“1” L
eve
l
Vin = V
CC
ÎÎ
Î
V
OH
Î
Î
—
—
—
5.0
10
15
Î
Î
4.95
9.95
14.95
Î
Î
—
—
—
Î
Î
4.95
9.95
14.95
ÎÎ
Î
5.0
10
15
Î
Î
—
—
—
4.95
9.95
14.95
Î
Î
—
—
—
Î
Î
Vdc
ООООООООО
Î
ООООООООО
Î
ООООООООО
Î
Input Voltage “0” Level
(VOL = 1.0 Vdc) TTL–CMOS
(V
OL
= 1.5 Vdc) TTL–CMOS
(VOL = 1.0 Vdc) CMOS–CMOS
(VOL = 1.5 Vdc) CMOS–CMOS
(VOL = 1.5 Vdc) CMOS–CMOS
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
V
IL
Î
Î
Î
Î
Î
Î
5.0
5.0
5.0
5.0
10
10
15
10
15
15
Î
Î
Î
Î
Î
Î
—
—
—
—
—
Î
Î
Î
Î
Î
Î
0.8
0.8
1.5
1.5
3.0
Î
Î
Î
Î
Î
Î
—
—
—
—
—
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
1.3
1.3
2.25
2.25
4.5
Î
Î
Î
Î
Î
Î
0.8
0.8
1.5
1.5
3.0
—
—
—
—
—
Î
Î
Î
Î
Î
Î
0.8
0.8
1.4
1.5
2.9
Î
Î
Î
Î
Î
Î
Vdc
ООООООООО
Î
ООООООООО
Î
ООООООООО
Î
Input Voltage “1” Level
(V
OH
= 9.0 Vdc) TTL–CMOS
(VOH = 13.5 Vdc) TTL–CMOS
(VOH = 9.0 Vdc) CMOS–CMOS
(V
OH
= 13.5 Vdc) CMOS–CMOS
(VOH = 13.5 Vdc) CMOS–CMOS
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
V
IH
Î
Î
Î
Î
Î
Î
5.0
5.0
5.0
5.0
10
10
15
10
15
15
Î
Î
Î
Î
Î
Î
2.0
2.0
3.6
3.6
7.1
Î
Î
Î
Î
Î
Î
—
—
—
—
—
Î
Î
Î
Î
Î
Î
2.0
2.0
3.5
3.5
7.0
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
1.5
1.5
2.75
2.75
5.5
Î
Î
Î
Î
Î
Î
—
—
—
—
—
2.0
2.0
3.5
3.5
7.0
Î
Î
Î
Î
Î
Î
—
—
—
—
—
Î
Î
Î
Î
Î
Î
Vdc
ООООООООО
Î
ООООООООО
Î
ООООООООО
Î
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(VOH = 13.5 Vdc)
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
I
OH
Î
Î
Î
Î
Î
Î
—
—
—
—
5.0
5.0
10
15
Î
Î
Î
Î
Î
Î
– 3.0
–0.64
– 1.6
– 4.2
Î
Î
Î
Î
Î
Î
—
—
—
—
Î
Î
Î
Î
Î
Î
– 2.4
–0.51
– 1.3
– 3.4
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
– 4.2
– 0.88
– 2.25
– 8.8
Î
Î
Î
Î
Î
Î
—
—
—
—
– 1.7
–0.36
– 0.9
– 2.4
Î
Î
Î
Î
Î
Î
—
—
—
—
Î
Î
Î
Î
Î
Î
mAdc
ООООООООО
Î
(VOL = 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
ÎÎ
Î
I
OL
Î
Î
—
—
—
5.0
10
15
Î
Î
0.64
1.6
4.2
Î
Î
—
—
—
Î
Î
0.51
1.3
3.4
ÎÎ
Î
0.88
2.25
8.8
Î
Î
—
—
—
0.36
0.9
2.4
Î
Î
—
—
—
Î
Î
mAdc
Input Current
I
in
—
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance (Vin = 0)
C
in
—
—
—
—
—
5.0
7.5
—
—
pF
ООООООООО
Î
ООООООООО
Î
Quiescent Current
(Per Package)
CMOS–CMOS Mode
ÎÎ
Î
ÎÎ
Î
IDD or
I
CC
Î
Î
Î
Î
—
—
—
5.0
10
15
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
0.05
0.10
0.20
Î
Î
Î
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
0.0005
0.0010
0.0015
Î
Î
Î
Î
0.05
0.10
0.20
—
—
—
Î
Î
Î
Î
1.5
3.0
6.0
Î
Î
Î
Î
µAdc
ООООООООО
Î
Quiescent Current
(Per Package)
TTL–CMOS Mode
ÎÎ
Î
I
DD
Î
Î
5.0
5.0
5.0
5.0
10
15
Î
Î
—
—
—
Î
Î
0.5
1.0
2.0
Î
Î
—
—
—
ÎÎ
Î
0.0005
0.0010
0.0015
Î
Î
0.5
1.0
2.0
—
—
—
Î
Î
3.8
7.5
15
Î
Î
µAdc
ООООООООО
Î
Quiescent Current
(Per Package)
TTL–CMOS Mode
ÎÎ
Î
I
CC
Î
Î
5.0
5.0
5.0
5.0
10
15
Î
Î
—
—
—
Î
Î
5.0
5.0
5.0
Î
Î
—
—
—
ÎÎ
Î
2.5
2.5
2.5
Î
Î
5.0
5.0
5.0
—
—
—
Î
Î
6.0
6.0
6.0
Î
Î
mAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 4
MC14504B
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4
SWITCHING CHARACTERISTICS (C
L
= 50 pF, TA = 25_C)
V
CC
V
DD
Limits
Characteristic
Symbol
Shifting Mode
CC
Vdc
DD
Vdc
Min
Typ
(5.)
Max
Unit
ОООООООО
Î
Propagation Delay, High to Low
ÎÎÎ
Î
t
PHL
ÎÎÎÎ
Î
TTL – CMOS
V
DD
> V
CC
Î
Î
5.0
5.0
ÎÎ
Î
10
15
Î
Î
—
—
ÎÎ
Î
140
140
Î
Î
280
280
Î
Î
ns
ООООООООÎÎÎÎÎÎÎÎÎ
Î
CMOS – CMOS
V
DD
> V
CC
Î
Î
5.0
5.0
10
ÎÎ
Î
10
15
15
Î
Î
—
—
—
ÎÎ
Î
120
120
70
Î
Î
240
240
140
Î
Î
ООООООООÎÎÎÎÎÎÎÎÎ
Î
CMOS – CMOS
V
CC
> V
DD
Î
Î
10
15
15
ÎÎ
Î
5.0
5.0
10
Î
Î
—
—
—
ÎÎ
Î
185
185
175
Î
Î
370
370
350
Î
Î
ОООООООО
Î
Propagation Delay, Low to High
ÎÎÎ
Î
t
PLH
ÎÎÎÎ
Î
TTL – CMOS
V
DD
> V
CC
Î
Î
5.0
5.0
ÎÎ
Î
10
15
Î
Î
—
—
ÎÎ
Î
170
160
Î
Î
340
320
Î
Î
ns
ООООООООÎÎÎÎÎÎÎÎÎ
Î
CMOS – CMOS
V
DD
> V
CC
Î
Î
5.0
5.0
10
ÎÎ
Î
10
15
15
Î
Î
—
—
—
ÎÎ
Î
170
170
100
Î
Î
340
340
200
Î
Î
ООООООООÎÎÎÎÎÎÎÎÎ
Î
CMOS – CMOS
V
CC
> V
DD
Î
Î
10
15
15
ÎÎ
Î
5.0
5.0
10
Î
Î
—
—
—
ÎÎ
Î
275
275
145
Î
Î
550
550
290
Î
Î
ОООООООО
Î
Output Rise and Fall Time
ÎÎÎ
Î
t
TLH
, t
THL
ÎÎÎÎ
Î
ALL
Î
Î
—
—
—
ÎÎ
Î
5.0
10
15
Î
Î
—
—
—
ÎÎ
Î
100
50
40
Î
Î
200
100
80
Î
Î
ns
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 5
MC14504B
http://onsemi.com
5
Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TTL to CMOS Mode
Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary TTL to CMOS Mode
20151050
V
DD
, SUPPLY VOLTAGE (Vdc)
7
6
5
4
3
2
1
0
V
Sp
, INPUT SWITCHPOINT VOLTAGE (Vdc)
20151050
V
DD
, SUPPLY VOLTAGE (Vdc)
7
6
5
4
3
2
1
0
V
Sp
, INPUT SWITCHPOINT VOLTAGE (Vdc)
VCC = 10 V
V
CC
= 5 V
V
CC
= 5 V
V
DD
, SUPPLY VOLTAGE (Vdc)
20
15
10
5
0
20151050
V
CC
, SUPPLY VOLTAGE (Vdc)
V
DD
, SUPPLY VOLTAGE (Vdc)
20
15
10
5
0
20151050
V
CC
, SUPPLY VOLTAGE (Vdc)
Page 6
MC14504B
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6
P ACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
Page 7
MC14504B
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7
P ACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
____
SECTION N–N
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
Page 8
MC14504B
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8
P ACKAGE DIMENSIONS
H
E
A
1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
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