Datasheet MC14503BFR1, MC14503BD, MC14503BF, MC14503BFEL, MC14503BFL2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14503B/D

MC14503B

Hex Non-Inverting 3-State
Buffer

The MC14503B is a hex non–inverting buffer with 3–state outputs,
and a high current source and sink capability. The 3–state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a
high impedance state.

• 3–State Outputs

• TTL Compatible — Will Drive One TTL Load Over Full

Temperature Range

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Two Disable Controls for Added Versatility

• Pin for Pin Replacement for MM80C97 and 340097

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

I

in

Input Current

(DC or Transient) per Pin

±10 mA

I

out

Output Current

(DC or Transient) per Pin

±25 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

http://onsemi.com

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14503BCP PDIP–16 2000/Box
MC14503BD SOIC–16 48/Rail
MC14503BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14503BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14503B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14503B

AWLYWW

MC14503BF SOEIAJ–16 See Note 1.
MC14503BFEL SOEIAJ–16 See Note 1.

MC14503B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

IN 5

OUT 6

IN 6

V

DD

OUT 4

IN 4

OUT 5

IN 2

OUT 1

IN 1

DIS A

V

SS

OUT 3

IN 3

OUT 2

DIS B

LOGIC DIAGRAMTRUTH TABLE

Appropriate

Disable

In

n

Input Out

n

00 0
10 1
X 1 High

Impedance

X = Don’t Care

DISABLE B

OUT 5

15
12
14

2
4
6

10

1

IN 5
IN 6
IN 1
IN 2

IN 3
IN 4

DISABLE A

OUT 6
OUT 1
OUT 2
OUT 3
OUT 4

11
13

3
5
7
9

V

DD

= PIN 16

V

SS

= PIN 8

CIRCUIT DIAGRAM

*IN

n

*DISABLE

*INPUT

TO OTHER BUFFERS

V

SS

V

DD

OUT

n

*Diode protection on all inputs (not shown)

ONE OF TWO/FOUR BUFFERS

MC14503B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

“1” Level

V

in

= V

DD

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 3.6 or 1.4 Vdc)

(V

O

= 7.2 or 2.8 Vdc)

(V

O

= 11.5 or 3.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

“1” Level

(V

O

= 1.4 or 3.6 Vdc)

(V

O

= 2.8 or 7.2 Vdc)

(V

O

= 3.5 or 11.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 2.5 Vdc)

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

Î

Î

Î

Î

4.5

5.0

5.0
10
15

Î

Î

Î

Î

Î

Î

Î

Î

– 4.3
– 5.8
– 1.2
– 3.1
– 8.2

Î

Î

Î

Î

Î

Î

Î

Î

—
—
—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 3.6
– 4.8

– 1.02

– 2.6
– 6.8

Î

Î

Î

Î

Î

Î

Î

Î

– 5.0
– 6.1
– 1.4
– 3.7

– 14.1

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—
—
—

Î

Î

Î

Î

Î

Î

Î

Î

– 2.5
– 3.0
– 0.7
– 1.8
– 4.8

Î

Î

Î

Î

Î

Î

Î

Î

—
—
—
—
—

Î

Î

Î

Î

Î

Î

Î

Î

mAdc

ОООООООО

Î

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.4 Vdc)

(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OL

Î

Î

Î

Î

4.5

5.0
10
15

Î

Î

Î

Î

2.2

2.6

6.5

19.2

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

1.8

2.1

5.5

16.1

Î

Î

Î

Î

2.1

2.3

6.2
25

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

1.2

1.3

3.8

11.2

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

(V

in

= 0)

C

in

—

—

—

—

5.0

7.5

—

—

pF

ОООООООО

Î

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

ÎÎ

Î

I

Q

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.0

2.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.002

0.004

0.006

ÎÎ

Î

ÎÎ

Î

1.0

2.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

30
60

120

Î

Î

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs)
(All outputs switching,
50% Duty Cycle)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (2.5 µA/kHz) f + I

DD

IT = (6.0 µA/kHz) f + I

DD

IT = (10 µA/kHz) f + I

DD

Î

Î

Î

Î

Î

Î

µAdc

ОООООООО

Î

Three–State Output Leakage

Current

ÎÎ

Î

I

TL

Î

Î

15

Î

Î

—

Î

Î

± 0.1

ÎÎ

Î

—

Î

Î

± 0.0001

ÎÎ

Î

± 0.1

Î

Î

—

Î

Î

± 3.0

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

MC14503B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

V

All Types

Characteristic

Symbol

V

DD

V

CC

Typ

(8.)

Max

Unit

ОООООООООООООО

Î

ОООООООООООООО

Î

Output Rise Time

t

TLH

= (0.5 ns/pF) CL + 20 ns

t

TLH

= (0.3 ns/pF) CL + 8.0 ns

t

TLH

= (0.2 ns/pF) CL + 8.0 ns

ÎÎÎÎ

Î

ÎÎÎÎ

Î

t

TLH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

45
23
18

ÎÎ

Î

ÎÎ

Î

90
45
35

ÎÎ

Î

ÎÎ

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

Output Fall Time

t

THL

= (0.5 ns/pF) CL + 20 ns

t

THL

= (0.3 ns/pF) CL + 8.0 ns

t

THL

= (0.2 ns/pF) CL + 8.0 ns

ÎÎÎÎ

Î

ÎÎÎÎ

Î

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

45
23
18

ÎÎ

Î

ÎÎ

Î

90
45
35

ÎÎ

Î

ÎÎ

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

Turn–Off Delay Time, all Outputs

t

PLH

= (0.3 ns/pF) CL + 60 ns

t

PLH

= (0.15 ns/pF) CL + 27 ns

t

PLH

= (0.1 ns/pF) CL + 20 ns

ÎÎÎÎ

Î

ÎÎÎÎ

Î

t

PLH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

75
35
25

ÎÎ

Î

ÎÎ

Î

150

70
50

ÎÎ

Î

ÎÎ

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

Turn–On Delay Time, all Outputs

t

PHL

= (0.3 ns/pF) CL + 60 ns

t

PHL

= (0.15 ns/pF) CL + 27 ns

t

PHL

= (0.1 ns/pF) CL + 20 ns

ÎÎÎÎ

Î

ÎÎÎÎ

Î

t

PHL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

75
35
25

ÎÎ

Î

ÎÎ

Î

150

70
50

ÎÎ

Î

ÎÎ

Î

ns

ОООООООООООООО

Î

3–State Propagation Delay Time

Output “1” to High Impedance

ÎÎÎÎ

Î

t

PHZ

ÎÎ

Î

5.0
10
15

ÎÎ

Î

75
40
35

ÎÎ

Î

150

80
70

ÎÎ

Î

ns

ОООООООООООООО

Î

Output “0” to High Impedance

ÎÎÎÎ

Î

t

PLZ

ÎÎ

Î

5.0
10
15

ÎÎ

Î

80
40
35

ÎÎ

Î

160

80
70

ÎÎ

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

High Impedance to “1” Level

ÎÎÎÎ

Î

ÎÎÎÎ

Î

t

PZH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

65
25
20

ÎÎ

Î

ÎÎ

Î

130

50
40

ÎÎ

Î

ÎÎ

Î

ns

ОООООООООООООО

Î

High Impedance to “0” Level

ÎÎÎÎ

Î

t

PZL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

100

35
25

ÎÎ

Î

200

70
50

ÎÎ

Î

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Switching Time Test Circuit and Waveforms

(t

TLH

, t

THL

, t

PHL

, and t

PLH

)

PULSE

GENERATOR

DISABLE

INPUT

INPUT

V

DD

16

V

SS

C

L

OUTPUT

20 ns 20 ns

V

DD

V

SS

V

OH

V

OL

t

PHL

t

THL

t

TLH

t

PLH

90%

50%

10%

OUTPUT

INPUT

t

PLH

t

PHL

90%

50%

10%

MC14503B

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5

Figure 2. 3–State AC Test Circuit and Waveforms

(t

PLZ

, t

PHZ

, t

PZH

, t

PZL

)

PULSE

GENERATOR

DISABLE INPUT

16

V

SS

1 k

OUTPUT

20 ns 20 ns

V

DD

50%

90%

V

DD

1k

8

INPUT

t

PHZ

, t

PZH

CIRCUIT

PULSE

GENERATOR

DISABLE INPUT

t

PLZ

, t

PZL

CIRCUIT

OUTPUT

V

SS

8

16

INPUT

C

L

C

L

V

DD

V

SS

V

OH

V

OL

≈ VOL + 0.05 V

≈ V

OH

– 0.15 V

10%

90%

10%

90%

10%

t

PLZ

t

PHZ

t

PZH

t

PZL

OUTPUT FOR t

PZH

, t

PZL

CIRCUIT

OUTPUT FOR t

PHZ

, t

PLZ

CIRCUIT

DISABLE INPUT

MC14503B

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6

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14503B

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7

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14503B

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