Page 1
MOTOROLA CMOS LOGIC DATAMC14503B
326
The MC14503B is a hex non–inverting buffer with 3–state outputs, and a
high current source and sink capability . The 3–state outputs make it useful in
common bussing applications. Two disable controls are provided. A high
level on the Disable A input causes the outputs of buffers 1 through 4 to go
into a high impedance state and a high level on the Disable B input causes
the outputs of buffers 5 and 6 to go into a high impedance state.
• 3–State Outputs
• TTL Compatible — Will Drive One TTL Load Over Full Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Two Disable Controls for Added Versatility
• Pin for Pin Replacement for MM80C97 and 340097
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
I
in
Input Current (DC or Transient), per Pin
± 10
mA
I
out
Output Current (DC or Transient), per Pin
± 25
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT DIAGRAM
*IN
n
*DISABLE
*INPUT
TO OTHER BUFFERS
V
SS
V
DD
OUT
n
*Diode protection on all inputs (not shown)
ONE OF TWO/FOUR BUFFERS
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
LOGIC DIAGRAM
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TRUTH TABLE
Appropriate
Disable
In
n
Input Out
n
0 0 0
1 0 1
X 1 High
Impedance
X = Don’t Care
DISABLE B
OUT 5
15
12
14
2
4
6
10
1
IN 5
IN 6
IN 1
IN 2
IN 3
IN 4
DISABLE A
OUT 6
OUT 1
OUT 2
OUT 3
OUT 4
11
13
3
5
7
9
VDD = PIN 16
VSS = PIN 8
Page 2
MOTOROLA CMOS LOGIC DATA
327
MC14503B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.0
4.0
Vdc
“1” Level
(VO = 1.4 or 3.6 Vdc)
(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
4.5
5.0
5.0
10
15
– 4.3
– 5.8
– 1.2
– 3.1
– 8.2
—
—
—
—
—
– 3.6
– 4.8
– 1.02
– 2.6
– 6.8
– 5.0
– 6.1
– 1.4
– 3.7
– 14.1
—
—
—
—
—
– 2.5
– 3.0
– 0.7
– 1.8
– 4.8
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
4.5
5.0
10
15
2.2
2.6
6.5
19.2
—
—
—
—
1.8
2.1
5.5
16.1
2.1
2.3
6.2
25
—
—
—
—
1.2
1.3
3.8
11.2
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
Q
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
30
60
120
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs)
(All outputs switching,
50% Duty Cycle)
I
T
5.0
10
15
IT = (2.5 µA/kHz) f + I
DD
IT = (6.0 µA/kHz) f + I
DD
IT = (10 µA/kHz) f + I
DD
µAdc
Three–State Output Leakage
Current
I
TL
15
—
± 0.1
—
± 0.0001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.
Page 3
MOTOROLA CMOS LOGIC DATAMC14503B
328
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
V
All Types
Characteristic
Symbol
V
DD
V
CC
Typ #
Max
Unit
Output Rise Time
t
TLH
= (0.5 ns/pF) CL + 20 ns
t
TLH
= (0.3 ns/pF) CL + 8.0 ns
t
TLH
= (0.2 ns/pF) CL + 8.0 ns
t
TLH
5.0
10
15
45
23
18
90
45
35
ns
Output Fall Time
t
THL
= (0.5 ns/pF) CL + 20 ns
t
THL
= (0.3 ns/pF) CL + 8.0 ns
t
THL
= (0.2 ns/pF) CL + 8.0 ns
t
THL
5.0
10
15
45
23
18
90
45
35
ns
Turn–Off Delay Time, all Outputs
t
PLH
= (0.3 ns/pF) CL + 60 ns
t
PLH
= (0.15 ns/pF) CL + 27 ns
t
PLH
= (0.1 ns/pF) CL + 20 ns
t
PLH
5.0
10
15
75
35
25
150
70
50
ns
Turn–On Delay Time, all Outputs
t
PHL
= (0.3 ns/pF) CL + 60 ns
t
PHL
= (0.15 ns/pF) CL + 27 ns
t
PHL
= (0.1 ns/pF) CL + 20 ns
t
PHL
5.0
10
15
75
35
25
150
70
50
ns
3–State Propagation Delay Time
Output “1” to High Impedance
t
PHZ
5.0
10
15
75
40
35
150
80
70
ns
Output “0” to High Impedance
t
PLZ
5.0
10
15
80
40
35
160
80
70
ns
High Impedance to “1” Level
t
PZH
5.0
10
15
65
25
20
130
50
40
ns
High Impedance to “0” Level
t
PZL
5.0
10
15
100
35
25
200
70
50
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
IN 5
OUT 6
IN 6
V
DD
OUT 4
IN 4
OUT 5
IN 2
OUT 1
IN 1
DIS A
V
SS
OUT 3
IN 3
OUT 2
DIS B
Page 4
MOTOROLA CMOS LOGIC DATA
329
MC14503B
Figure 1. Switching Time Test Circuit and Waveforms
(t
TLH
, t
THL
, t
PHL
, and t
PLH
)
PULSE
GENERATOR
DISABLE
INPUT
INPUT
V
DD
16
V
SS
C
L
OUTPUT
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
t
PHL
t
THL
t
TLH
t
PLH
90%
50%
10%
OUTPUT
INPUT
t
PLH
t
PHL
90%
50%
10%
Figure 2. 3–State AC Test Circuit and Waveforms
(t
PLZ
, t
PHZ
, t
PZH
, t
PZL
)
PULSE
GENERATOR
DISABLE INPUT
16
V
SS
1 k
OUTPUT
20 ns 20 ns
V
DD
50%
90%
V
DD
1 k
8
INPUT
t
PHZ
, t
PZH
CIRCUIT
PULSE
GENERATOR
DISABLE INPUT
t
PLZ
, t
PZL
CIRCUIT
OUTPUT
VSS8
16
INPUT
C
L
C
L
V
DD
V
SS
V
OH
V
OL
≈
VOL + 0.05 V
≈
VOH – 0.15 V
10%
90%
10%
90%
10%
t
PLZ
t
PHZ
t
PZH
t
PZL
OUTPUT FOR t
PZH
, t
PZL
CIRCUIT
OUTPUT FOR t
PHZ
, t
PLZ
CIRCUIT
DISABLE INPUT
Page 5
MOTOROLA CMOS LOGIC DATAMC14503B
330
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATA
331
MC14503B
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14503B/D
*MC14503B/D*
◊
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