Datasheet MC14502BCL, MC14502BCP Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATAMC14502B

320

  

The MC14502B is a strobed hex buffer/inverter with 3–state outputs, an inhibit control, and guaranteed TTL drive over the temperature range. The 3–state output simplifies design by allowing a common bus.

• Separate Output Disable Control

• 3–State Output

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving 4LSTTL Loads Over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

I

in

Input Current (DC or Transient), per Pin

± 10

mA

I

out

Output Current (DC or Transient), per Pin

+ 30

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

CIRCUIT DIAGRAM

DISABLE

INHIBIT

D1

V

DD

V

SS

Q1

Other five buffers are identical

TRUTH TABLE

D

n

Inhibit Disable Q

n

0 0 0 1 1 0 0 0 X 1 0 0 X X 1 High

Impedance

X = Don’t Care



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC CASE 620

ORDERING INFORMATION

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

LOGIC DIAGRAM

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC

14 Q6

11 Q5

9 Q4

2 Q3

7 Q2

5 Q1

3–STATE OUTPUT DISABLE

INHIBIT 12

4

D1 3

D2 6

D3 1

D4 10

D5 13

D6 15

VDD = PIN 16

VSS = PIN 8

MOTOROLA CMOS LOGIC DATA

321

MC14502B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0”’ Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

V

IL

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

V

IH

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

I

OH

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

I

OL

5.0 10 15

3.5

7.8 29

— — —

2.8

6.3 24

6.6 17 66

— — —

2.0

4.4 16

ÎÎÎ

— — —

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

5.0

7.5

—

ÎÎÎ

—

pF

Quiescent Current

(Per Package)

I

DD

5.0 10 15

— — —

1.0

2.0

4.0

— — —

0.002

0.004

0.006

1.0

2.0

4.0

— — —

ÎÎÎ

30 60

120

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

I

T

5.0 10 15

IT = (2.7 µA/kHz) f + I

DD

IT = (5.3 µA/kHz) f + I

DD

IT = (8.0 µA/kHz) f + I

DD

µAdc

Three–State Leakage Current

I

TL

15

—

± 0.1

—

± 0.0001

± 0.1

—

ÎÎÎ

± 3.0

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

INH

D5

Q6

V

DD

Q4

D4

Q5

DISABLE

D1

Q3

D3

V

SS

Q2

D2

Q1

D6

MOTOROLA CMOS LOGIC DATAMC14502B

322

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

ÎÎÎÎ

ОООООООООО

All Types

Characteristic

ÎÎÎÎ

Symbol

V

DD

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise Time

ÎÎÎÎ

t

TLH

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

80

ns

Output Fall Time

ÎÎÎÎ

t

THL

5.0 10 15

ÎÎÎÎ

— — —

40 20 15

80 40 30

ns

Propagation Delay Time Data to Q

ÎÎÎÎ

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

135

55 40

270 110

80

ns

Propagation Delay Time, Inhibit to Q

ÎÎÎÎ

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

335 145

95

670 290 190

ns

Propagation Delay Time Data to Q, Inhibit to Q

ÎÎÎÎ

t

PLH

5.0 10 15

ÎÎÎÎ

— — —

295 130

95

590 260 190

ns

3–State Propagation Delay, Output “1” to High Impedance

ÎÎÎÎ

t

PHZ

5.0 10 15

ÎÎÎÎ

— — —

65 30 25

130

60 50

ns

3–State Propagation Delay, High Impedance to “1” Level

ÎÎÎÎ

t

PZH

5.0 10 15

ÎÎÎÎ

— — —

260 105

80

520 210 160

ns

3–State Propagation Delay, Output “0” to High Impedance

ÎÎÎÎ

t

PLZ

5.0 10 15

ÎÎÎÎ

— — —

150

70 55

300 140 110

ns

3–State Propagation Delay, High Impedance to “0” Level

ÎÎÎÎ

t

PZL

5.0 10 15

ÎÎÎÎ

— — —

160

65 50

320 130 100

ns

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Typical Output Source

Current Test Circuit (IOH)

Figure 2. Typical Output Sink

Current Test Circuit (IOL)

16 + V

DD

DIS INH D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

8

V

SS

V

OH

I

OH

V

out

VGS = –V

DD

VDS = VOH – V

DD

DIS INH D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

I

OL

V

OL

V

out

16 + V

DD

8

V

SS

VDS = V

OL

VGS = V

DD

MOTOROLA CMOS LOGIC DATA

323

MC14502B

Figure 3. Power Dissipation Test Circuit and Waveform

DIS INH D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

V

DD

I

D

PULSE

GENERATOR

C

L

C

L

C

L

C

L

C

L

C

L

V

in

20 ns 20 ns

V

DD

V

SS

90%

50%

10%

50% DUTY CYCLE

Figure 4. AC Test Circuit and Waveforms

(t

TLH

, t

THL

, T

PLH

, and t

PHL

)

Figure 5. 3–State AC Test Circuit and Waveforms

(t

PHZ

, t

PLZ

, t

PZH

, t

PZL

)

Switch Positions for 3–State Test

Test S1 S2 S3 S4

t

PHZ

Open Closed Closed Open

t

PLZ

Closed Open Open Closed

t

PZL

Closed Open Open Closed

t

PZH

Open Closed Closed Open

DISABLE INHIBIT D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

C

L

16 V

DD

8

V

SS

PULSE

GENERATOR

20 ns 20 ns

V

DD

V

SS

V

OH

V

OL

90%

10%

50%

90%

10%

t

PLH

t

PHL

t

THL

t

TLH

OUTPUT

(TESTS 1 AND 2)

For all t

TLH

, t

THL

, t

PHL

, and t

PLH

measurements V

in

may be applied to any other Dn input or to inhibit.

16 V

DD

PULSE

GENERATOR

V

DD

C

L

1 k

S1

S2

V

DD

S4

S3

8

V

SS

DISABLE INHIBIT D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

20 ns 20 ns

V

DD

V

SS

V

OH

t

PLZ

t

PHZ

t

PZH

t

PZL

50%

90%

10%

90%

10%

90%

≈

0.5 V @ VDD = 5 V, 10 V, AND 15 V

≈

2 V @ VDD = 5 V

≈

6 V @ VDD = 10 V

≈

10 V @ VDD = 15 V

V

OL

INPUT

DISABLE

Q OUTPUTS

MOTOROLA CMOS LOGIC DATAMC14502B

324

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

325

MC14502B

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

M

B

M

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

–A–

–B– P8X

G14X

D16X

SEATING PLANE

–T–

S

A

M

0.010 (0.25) B

S

T

16 9

81

F

J

R

X 45

_

_ _ _ _

M

C

K

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer .

MC14502B/D

*MC14502B/D*

◊

Datasheet MC14502BCL, MC14502BCP Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

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