Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14501UB
Dual 4–Input “NAND” Gate
2–Input “NOR/OR” Gate
8–Input “AND/NAND” Gate
The MC14501UB is constructed with MOS P–channel and N–channel
enhancement mode d evices in a s ingle m onolithic structure. These
complementary MOS logic gates find p rimary use where low p ower
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin,
Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC
(5) 4
(9) 3
(7) 2
(6) 1
13 (10)
VDD16
VSS8
V
DD
11
12
14
15
V
SS
V
SS
Numbers in parenthesis are for second 4–input gate.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
LOGIC DIAGRAM
(POSITIVE LOGIC)
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
1
2
3
4
11
12
5
6
7
9
13
14 AND
15 NAND
10
VDD = PIN 16
VSS = PIN 8
Use Dotted Connection Externally to
Obtain 8–Input AND/NAND
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
Page 2
MOTOROLA CMOS LOGIC DATAMC14501UB
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
3.75
—
—
—
2.25
4.50
6.75
1.5
3.0
3.75
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.4
2.9
3.6
Vdc
(VO = 1.4 or 3.6 Vdc)
“1” Level
(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)
V
IH
5.0
10
15
3.6
7.1
11.4
—
—
—
3.5
7.0
11.25
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc) NAND*
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOH = 2.5 Vdc) NOR
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc
(VOH = 13.5 Vdc)
5.0
5.0
10
15
– 2.1
– 0.42
– 1.06
– 3.1
—
—
—
—
– 1.75
– 0.35
– 0.88
– 2.63
– 3.0
– 0.63
– 1.58
– 6.12
—
—
—
—
– 1.22
– 0.24
– 0.62
– 1.84
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOH = 2.5 Vdc) NOR–
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc) Inverter
(VOH = 13.5 Vdc)
5.0
5.0
10
15
– 3.6
– 0.72
– 1.8
– 5.4
—
—
—
—
– 3.0
– 0.6
– 1.5
– 4.5
– 5.1
– 1.08
– 2.7
– 10.5
—
—
—
—
– 2.1
– 0.42
– 1.05
– 3.15
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
OH
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc) NAND*
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
OL
= 1.5 Vdc)
(VOL = 0.4 Vdc) NOR
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
5.0
10
15
0.92
2.34
6.12
—
—
—
0.77
1.95
5.1
1.32
3.37
13.2
—
—
—
0.54
1.36
3.57
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
OL
= 1.5 Vdc)
(VOL = 0.4 Vdc) NOR–
(VOL = 0.5 Vdc) Inverter
(VOL = 1.5 Vdc)
5.0
10
15
1.54
3.90
10.2
—
—
—
1.28
3.25
8.5
2.2
5.63
22
—
—
—
0.90
2.27
5.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.2 µA/kHz) f + I
DD
IT = (2.4 µA/kHz) f + I
DD
IT = (3.6 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14501UB
SWITCHING CHARACTERISTICS** (C
L
= 50 pF, TA = 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Figure
Symbol
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
V
DD
Typ #
Max
Unit
Output Rise Time NAND, NOR
t
TLH
= (3.0 ns/pF) CL + 30 ns
t
TLH
= (1.5 ns/pF) CL + 15 ns
t
TLH
= (1.1 ns/pF) CL + 10 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2, 3
t
TLH
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
180
90
65
360
180
130
ns
Output Fall Time NAND, NOR
t
THL
= (1.5 ns/pF) CL + 25 ns
t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
THL
= (0.55 ns/pF) CL + 9.5 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2, 3
t
THL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
100
50
40
200
100
80
ns
Output Rise Time NOR–Inverter
t
TLH
= (1.35 ns/pF) CL + 32.5 ns
t
TLH
= (0.60 ns/pF) CL + 20 ns
t
TLH
= (0.40 ns/pF) CL + 17 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3
t
TLH
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time NOR–Inverter
t
THL
= (0.67 ns/pF) CL + 26.5 ns
t
THL
= (0.45 ns/pF) CL + 17.5 ns
t
THL
= (0.37 ns/pF) CL + 11.5 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3
t
THL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
60
40
30
120
80
60
ns
Propagation Delay Time NAND
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 45 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 37 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 25 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2
t
PLH
,
t
PHL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
50
10
15
130
70
50
260
140
100
ns
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 30 ns NOR
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 32 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 20 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3
t
PLH
t
PHL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
115
65
45
230
130
90
ns
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 45 ns
NOR–Inverter
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 37 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 25 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3
t
PLH
,
t
PHL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
130
70
50
260
140
100
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
Page 4
MOTOROLA CMOS LOGIC DATAMC14501UB
4
Figure 1. Power Dissipation Test Circuit
and Waveform
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
IN 2
B
OUT
A
OUT
B
V
DD
IN 4
C
OUT
C
IN 1
B
IN 4
A
IN 3
A
IN 2
A
IN 1
A
V
SS
IN 3
C
IN 2
C
IN 1
C
OUT
B
PIN ASSIGNMENT
0.01µF CERAMIC
VDD16
V
in
C
L
C
L
C
L
C
L
8
I
DD
500
µ
F
50% DUTY CYCLE
V
DD
V
SS
20 ns
90%
10%
90%
10%
20 ns
V
in
Figure 2. Input “NAND” Gate Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
16
INPUT
(A)
8 V
SS
C
L
OUTPUT
(B)
20 ns 20 ns
V
DD
V
SS
90%
50%
10%
50%
90%
10%
OUTPUT (B)
INPUT (A)
t
PHL
t
PLH
V
OH
V
OL
t
THL
t
TLH
90%
50%
10%
90%
50%
10%
Figure 3. “NOR” Gate and “NOR–Inverter” Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
C
L
20 ns
V
DD
90%
OUTPUT (B)
t
THL
INPUT (A)
OUTPUT (C)
C
L
INPUT (A)
OUTPUT (B)
OUTPUT (C)
V
SS
V
OH
V
OL
V
OH
V
OL
50%
10%
t
TLH
t
PLH
t
PHL
50%
90%
10%
90%
50%
10%
t
PLH
t
TLH
t
THL
Output (B) = “NOR”
Output (C) = “NOR–Inverter”
All unused inputs
connected to ground.
t
PHL
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14501UB
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATAMC14501UB
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14501UB/D
*MC14501UB/D*
◊
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