Datasheet MC145018P Datasheet (Motorola)



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SEMICONDUCTOR TECHNICAL DATA

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High–Performance Silicon–Gate CMOS

The MC54/74HCT374A may be used as a level converter for

interfacing TTL or NMOS outputs to High–Speed CMOS inputs.

The HCT374A is identical in pinout to the LS374.

Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip–flops, but when Output Enable is high, the outputs are forced to the high–impedance state. Thus, data may be stored even when the outputs are not enabled.

The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 276 FETs or 69 Equivalent Gates

• Improvements over HCT374

— Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity

LOGIC DIAGRAM

3

D0

4

D1

7

D2

8

DATA

INPUTS

OUTPUT ENABLE

Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product

*Equivalent to a two–input NAND gate.

D3

13

D4

14

D5

17

D6

18

D7

11

CLOCK

1

Design Criteria

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

PIN 20 = V PIN 10 = GND

CC

Value

69

1.5

5.0

.0075

NONINVERTING

OUTPUTS

Units

ea.

ns

µW

pJ



J SUFFIX

20

1

20

1

20

1

20

1

20

1

ORDERING INFORMATION

MC54HCTXXXAJ MC74HCTXXXAN MC74HCTXXXADW MC74HCTXXXASD MC74HCTXXXADT

PIN ASSIGNMENT

OUTPUT

ENABLE

Q0 D0 D1

Q1 5 Q2 D2 D3 Q3

GND

FUNCTION TABLE

Inputs Output

Output Enable Clock D Q

LHH LLL L L,H, X No Change

HXXZ

X = don’t care Z = high impedance

CERAMIC PACKAGE

CASE 732–03

PLASTIC PACKAGE

CASE 738–03

SOIC PACKAGE

CASE 751D–04

SSOP PACKAGE

CASE 940C–03

TSSOP PACKAGE

CASE 948E–02

1 2

3 4

6 7 8 9 10

20 19

18 17 16 15 14 13 12

11

N SUFFIX

DW SUFFIX

SD SUFFIX

DT SUFFIX

Ceramic Plastic SOIC SSOP TSSOP

V

CC Q7 D7

D6 Q6

Q5 D5 D4 Q4 CLOCK

2/97

 Motorola, Inc. 1997

1

REV 7

MC54/74HCT374A

Î

MAXIMUM RATINGS*

Symbol

V

I I

Î

T

Î

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air,Plastic or Ceramic DIP†

D

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

SSOP or TSSOP Package†

(Ceramic DIP)

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

ÎÎÎÎ

450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260 300

ÎÎÎÎ

Unit

V V

V mA mA mA

mW

Î

_

C

Î

_

C

Î

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)

f

Parameter

Min

4.5 0

– 55

0

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

ÎÎ

V

IH

ÎÎ

V

IL

ÎÎ

V

OH

ÎÎ

ÎÎÎОООООООÎООООООО

V

OL

ÎÎ

ÎÎÎОООООООÎООООООО

I

in

ООООООО

Minimum High–Level Input

ООООООО

Voltage Maximum Low–Level Input

Voltage

ООООООО

Minimum High–Level Output Voltage

ООООООО

Maximum Low–Level Output

ООООООО

Voltage

Maximum Input Leakage Current

Parameter

Test Conditions

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

ООООООО

|I

| v 20 µA

out

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

ООООООО

out

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 6.0 mA

out

Vin = VIH or V

ООООООО

|I

| v 20 µA

out

Vin = VIH or V |I

| v 6.0 mA

out

IL

Vin = VCC or GND

Max

5.5

V

CC

+ 125

500

Unit

V V

_

C

ns

V

CC

V

ÎÎ

4.5

ÎÎ

5.5

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

4.5

ÎÎ

5.5

4.5

ÎÎ

5.5

Guaranteed Limit

– 55 to

25_C

ÎÎ

2.0

ÎÎ

2.0

0.8

ÎÎ

4.4

5.4

ÎÎ

3.98

0.1

ÎÎ

0.1

0.26

ÎÎ

± 0.1

v

85_C

ÎÎ

2.0

ÎÎ

2.0

0.8

ÎÎ

4.4

5.4

ÎÎ

3.84

0.1

ÎÎ

0.1

0.33

ÎÎ

± 1.0

v

125_C

ÎÎ

2.0

ÎÎ

2.0

0.8

ÎÎ

4.4

5.4

ÎÎ

3.7

0.1

ÎÎ

0.1

0.4

ÎÎ

± 1.0

Unit

Î

µA

V

MOTOROLA High–Speed CMOS Logic Data

2

DL129 — Rev 6

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Î

Current

Î

V

i

= V

CC

GND, Other Inputs

Î

Symbol

I

OZ

ÎÎ

I

CC

ÎÎ

Parameter

Maximum Three–State Leakage Current

ООООООО

Maximum Quiescent Supply Current (per Package)

ООООООО

Output in High–Impedance State Vin = VIL or V V

Vin = VCC or GND I

Test Conditions

ООООООО

= VCC or GND

out

= 0 µA

ООООООО

out

IH

V

CC

V

5.5

ÎÎ

5.5

ÎÎ

Guaranteed Limit

– 55 to

25_C

± 0.5

ÎÎ

4.0

ÎÎ

MC54/74HCT374A

v

85_C

± 5.0

40

125_C

± 10

ÎÎ

160

ÎÎ

Unit

µA

Î

µA

Î

∆I

CC

ÎÎÎООООООО

Additional Quiescent Supply Current

Vin = 2.4 V, Any One Input

or

V

= V

n

l

out

ООООООО

or GND

= 0 µA

Other In

uts

5.5

ÎÎ

≥ –55_C

2.9

ÎÎÎ

25_C to 125_C

2.4

ÎÎÎ

mA

Î

NOTE: 1. Total Supply Current = ICC + Σ∆ICC. NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (V

ÎÎÎОООООООООООООООООÎОООООООО

ÎÎ

Symbol

f

max

ÎÎ

t

PLH

t

PHL

ÎÎ

t

PLZ

t

PHZ

t

PZL

ÎÎ

t

PZH

t

TLH

t

THL

ÎÎ

C

out

ООООООООООООООООО

Maximum Clock Frequency (50% Duty Cycle)

ООООООООООООООООО

(Figures 1 and 4)

,

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ООООООООООООООООО

,

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

,

Maximum Propagation Delay, Output Enable to Q

ООООООООООООООООО

(Figures 2 and 5)

,

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ООООООООООООООООО

in

Maximum Input Capacitance Maximum Three–State Output Capacitance

(Output in High–Impedance State)

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

CC

Parameter

Guaranteed Limit

– 55 to

ÎÎ

25_C

30

ÎÎ

31

ÎÎ

30

ÎÎ

12

ÎÎ

10 15

ÎÎ

v

85_C

24

ÎÎ

39

ÎÎ

38

ÎÎ

15

ÎÎ

10 15

ÎÎ

v

125_C

20

ÎÎ

47

ÎÎ

45

ÎÎ

18

ÎÎ

10 15

Î

Unit

MHz

Î

pF pF

ns

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

C

PD

Power Dissipation Capacitance (Per Flip–Flop)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (V

ÎÎ

Symbol

t

su

ÎÎ

t

h

t

w

ÎÎ

tr, t

ÎÎ

High–Speed CMOS Logic Data DL129 — Rev 6

ООООООООООООООООО

Minimum Setup Time, Data to Clock

ООООООООООООООООО

Minimum Hold Time, Clock to Data

Minimum Pulse Width, Clock

ООООООООООООООООО

Maximum Input Rise and Fall Times

f

ООООООООООООООООО

(Figure 3)

(Figure 1)

= 5.0 V ± 10%, Input tr = tf = 6.0 ns)

CC

Parameter

Typical @ 25°C, VCC = 5.0 V

65

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

pF

Guaranteed Limit

– 55 to

ÎÎ

25_C

12

ÎÎ

5.0

12

ÎÎ

500

ÎÎ

v

85_C

15

ÎÎ

5.0

15

ÎÎ

500

ÎÎ

v

125_C

18

ÎÎ

5.0

18

ÎÎ

500

ÎÎ

Î

Unit

Î

ns

3 MOTOROLA

MC54/74HCT374A

SWITCHING WAVEFORMS

CLOCK

Q

90%

1.3 V

10%

2.7 V

1.3 V

0.3 V

t

r

t

w

t

1/f

max

PLH

t

TLH

Figure 1.

t

f

t

PHL

t

THL

DATA

CLOCK

V

CC

GND

1.3 V t

su

Figure 3.

TEST CIRCUITS

OUTPUT

ENABLE

VALID

1.3 V

3 V

1.3 V t

t

PLZ

PZL

Q

1.3 V

t

PZHtPHZ

10%

90%

GND HIGH

IMPEDANCE V

OL

V

OH

HIGH IMPEDANCE

Figure 2.

3 V

t

h

GND

3 V

GND

OUTPUT

DEVICE

UNDER

TEST

*Includes all probe and jig capacitance

Figure 4.

D0 D1 D2 D3 D4 D5 D6 D7

347813141718

DQ

C

11

CLOCK

OUTPUT

ENABLE

1

TEST POINT

CL*

DEVICE UNDER

TEST

TEST POINT

1 k

OUTPUT

*Includes all probe and jig capacitance

Ω

CL*

CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t

PLZ

PHZ

AND t

PZL

PZH

Figure 5.

EXPANDED LOGIC DIAGRAM

DQCDQCDQCDQCDQCDQCDQ

C

256912151619

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

MOTOROLA High–Speed CMOS Logic Data

4

DL129 — Rev 6

OUTLINE DIMENSIONS

MC54/74HCT374A

–T–

SEATING PLANE

CERAMIC PACKAGE

20

110

A

F

H

D

SEATING PLANE

–A–

20

1

E

FG

11

B

C

K

G

D

20 PL

N

11

B

10

K

N

0.25 (0.010) T

J

PLASTIC PACKAGE

M

J SUFFIX

CASE 732–03

ISSUE E

L

M

N SUFFIX

CASE 738–03

ISSUE E

C

M

A

L

J

20 PL

0.25 (0.010) T

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

A 23.88 25.15 0.940 0.990 B 6.60 7.49 0.260 0.295 C 3.81 5.08 0.150 0.200 D 0.38 0.56 0.015 0.022 F 1.40 1.65 0.055 0.065 G 2.54 BSC 0.100 BSC H 0.51 1.27 0.020 0.050 J 0.20 0.30 0.008 0.012 K 3.18 4.06 0.125 0.160 L 7.62 BSC 0.300 BSC M 0 15 0 15

____

N 0.25 1.02 0.010 0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022

M

B

E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC

M

M 0 15 0 15 N 0.51 1.010.020 0.040

INCHESMILLIMETERS

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

–A–

20

1

D20X

0.010 (0.25) B

18X

G

High–Speed CMOS Logic Data DL129 — Rev 6

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

11

–B–

P10X

0.010 (0.25)

10

M

S

A

T

S

C

SEATING

–T–

PLANE

K

M

J

F

ISSUE E

M

B

R

X 45

_

M

5 MOTOROLA

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009

M 0 7 0 7

__

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS

__

MC54/74HCT374A

20 11

L/2

L

PIN 1 IDENT

M

C

D

0.076 (0.003)

SEATING

–T–

PLANE

0.20 (0.008) T

K20X REF

0.12 (0.005) V

101

A

–V–

S

U

G

OUTLINE DIMENSIONS

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940C–03

ISSUE B

M

S

U

T

S

N

B

–U–

J

H

DETAIL E

0.25 (0.010)

M

F

DETAIL E

K

K1

SECTION N–N

J1

–W–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

MILLIMETERS

DIMAMIN MAX MIN MAX

7.07 7.33 0.278 0.288

B 5.20 5.38 0.205 0.212 C 1.73 1.99 0.068 0.078 D 0.05 0.21 0.002 0.008 F 0.63 0.95 0.024 0.037 G 0.65 BSC 0.026 BSC H 0.59 0.75 0.023 0.030 J 0.09 0.20 0.003 0.008

J1 0.09 0.16 0.003 0.006

K 0.25 0.38 0.010 0.015

K1 0.25 0.33 0.010 0.013

L 7.65 7.90 0.301 0.311 M 0 8 0 8

____

INCHES

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

U

ISSUE A

S

B

–U–

S

JJ1

SECTION N–N

N

DETAIL E

K

K1

0.25 (0.010)

F

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHES

6.60 0.260

–W–

MILLIMETERS

DIMAMIN MAX MIN MAX

6.40 0.252

B 4.30 4.50 0.169 0.177

––– –––

C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

20X REFK

S

U0.15 (0.006) T

2X

L/2

L

PIN 1 IDENT

110

S

U0.15 (0.006) T

0.10 (0.004) V

M

T

1120

A

–V–

C

D

G

H

0.100 (0.004)

SEATING

–T–

PLANE

MOTOROLA High–Speed CMOS Logic Data

6

DL129 — Rev 6

MC54/74HCT374A

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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◊

High–Speed CMOS Logic Data

7 MOTOROLA

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MC74HCT374A/D

DL129 — Rev 6

Datasheet MC145018P Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual