Datasheet MC145017P, MC74HCT573ADT, MC74HCT573ADW Datasheet (Motorola)

Download

Page 1



ÎÎÎ

SEMICONDUCTOR TECHNICAL DATA

     "     # 



   ! 

High–Performance Silicon–Gate CMOS

The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled.

The HCT573A is identical in function to the HCT373A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HCT573A is the noninverting version of the HC563A.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 10 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 234 FETs or 58.5 Equivalent Gates

— Improved Propagation Delays — 50% Lower Quiescent Power

LOGIC DIAGRAM

D0 D1 D2

DATA

INPUTS

D3 D4

D5 D6 D7

LATCH ENABLE

OUTPUT ENABLE

Design Criteria

Internal Gate Count*

219 3 4 5 6 7 8 9

11 1

16 15

14 13

PIN 20 = V PIN 10 = GND

NONINVERTING

Q3 Q4

Q5 Q6 Q7

Value

58.5

OUTPUTS

Units

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

ORDERING INFORMATION

MC74HCTXXXAN MC74HCTXXXADW MC74HCTXXXADT

Plastic SOIC TSSOP

PIN ASSIGNMENT

OUTPUT

ENABLE

D0 D1 D2

D3 5 D4 D5 D6

GND

1 2

3 4

6 7 8

9 10

20 19

18 17 16 15 14 13 12

V Q0

Q1 Q2 Q3 Q4 Q5 Q6 Q7

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change

HXXZ

X = Don’t Care Z = High Impedance

Internal Gate Propagation Delay Internal Gate Power Dissipation

ОООООООО

Speed Power Product

*Equivalent to a two–input NAND gate.

10/96

 Motorola, Inc. 1996

1.5

5.0

ÎÎ

0.0075

µW

ÎÎ

REV 7

Page 2

MC74HCT573A

Current

GND, Other Inputs

MAXIMUM RATINGS*

Symbol

I I

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

out

DC Input Current, per Pin

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air Plastic DIP†

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: –6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Vin, V

tr, t

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Symbol

ÎÎ

ÎÎÎОООООООÎООООООО

ÎÎ

∆I

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ООООООО

Minimum High–Level Input Voltage

Maximum Low–Level Input

ООООООО

Voltage Minimum High–Level Output

Voltage

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State

Leakage Current

ООООООО

Maximum Quiescent Supply

ООООООО

Current (per Package) Additional Quiescent Supply

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, TSSOP or SOIC Package)

Parameter

ООООООО

Test Conditions

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

out

= 0.1 V or VCC – 0.1 V

out

ООООООО

| v 20 µA

out

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 6.0 mA

out

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 6.0 mA

out

Vin = VCC or GND Output in High–Impedance State

Vin = VIL or V

ООООООО

= VCC or GND

out

Vin = VCC or GND

ООООООО

v 0 µA

out

Vin = 2.4 V, Any One Input

out

= 0 µA

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎÎ

450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260

Min

4.5 0

– 55

Max

5.5

+ 125

500

Unit

V V

V mA mA mA

Unit

ÎÎ

4.5

5.5

4.5

ÎÎ

5.5

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

5.5

ÎÎ

5.5

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Guaranteed Limit

– 55 to

ÎÎ

25_C

ÎÎ

± 0.1 ± 0.5

ÎÎ

≥ – 55_C

2.0

0.8

4.4

5.4

3.98

0.1

0.26

4.0

2.9

ÎÎ

85_C

2.0

0.8

ÎÎ

0.8

4.4

5.4

ÎÎ

3.84

0.1

ÎÎ

0.33

± 1.0 ± 5.0

ÎÎ

25_C to 125_C

ÎÎ

2.4

out

125_C

2.0

0.8

4.4

5.4

3.7

0.1

0.4

± 1.0

± 10

160

) v VCC.

Unit

µA µA

µA

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Page 3

MC74HCT573A

ÎÎÎÎ

ÎÎ ÎÎ

ÎÎ

ÎÎ ÎÎ

AC ELECTRICAL CHARACTERISTICS (V

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

– 55 to

ÎÎ

Symbol

PLH

PHL

ÎÎ

PLH

ÎÎ

PHL

PLZ,

ÎÎ

PHZ

TZL,

TZH

ÎÎ

TLH

THL

out

ÎÎ

ООООООООООООООООО

Maximum Propagation Delay, Input D to Output Q

(Figures 1 and 5)

ООООООООООООООООО

Maximum Propagation Delay, Latch Enable to Q

ООООООООООООООООО

(Figures 2 and 5)

Parameter

Maximum Propagation Delay, Output Enable to Q

ООООООООООООООООО

(Figures 3 and 6)

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ООООООООООООООООО

Maximum Output Transition Time, any Output

(Figures 1 and 5) Maximum Input Capacitance Maximum Three–State Output Capacitance

ООООООООООООООООО

(Output in High–Impedance State)

25_C

ÎÎ

10 15

ÎÎ

85_C

ÎÎ

10 15

ÎÎ

125_C

ÎÎ

10 15

ÎÎ

Unit

pF pF

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Enabled Output)*

f + ICC VCC. For load considerations, see Chapter 2 of the

TIMING REQUIREMENTS (V

Symbol

tr, t

Minimum Setup Time, Input D to Latch Enable

su t

Minimum Hold Time, Latch Enable to Input D

Minimum Pulse Width, Latch Enable

Maximum Input Rise and Fall Times

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Parameter

Fig.

4 4 2 1

– 55 to 25_C

Min

Max

5.0 15

500

Guaranteed Limit

85_C

Min

Max

5.0 19

500

Min

5.0 22

125_C

Max

500

Unit

ns ns ns ns

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

Page 4

MC74HCT573A

INPUT D

PLH

TLH

SWITCHING WAVEFORMS

2.7 V

1.3 V

0.3 V

90%

1.3 V

10%

PHL

THL

3.0 V

GND

Figure 1. Figure 2.

LATCH

ENABLE

1.3 V

PLH

PHL

3.0 V

GND

OUTPUT ENABLE

DEVICE UNDER

TEST

1.3 V t

PZLtPLZ

1.3 V t

PZHtPHZ

1.3 V

Figure 3. Figure 4.

TEST POINT

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

CL*

Figure 5. T est Circuit

TEST POINT

OUTPUT

1 k

CL*

Ω

CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t

10%

90%

PLZ

PHZ

3.0 V

GND HIGH

IMPEDANCE V

HIGH IMPEDANCE

AND t

PZL

AND t

PZH

INPUT D

LATCH

ENABLE

1.3 V

VALID

1.3 V

3.0 V GND

EXPANDED LOGIC DIAGRAM

D LE

*Includes all probe and jig capacitance

Figure 6. T est Circuit

MOTOROLA High–Speed CMOS Logic Data

LATCH ENABLE

OUTPUT ENABLE

DL129 — Rev 6

Page 5

–T–

SEATING PLANE

–A–

D20X

0.010 (0.25) B

18X

MC74HCT573A

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

J 20 PL

0.25 (0.010) T

20 PL

0.25 (0.010) T

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

–B–

P10X

0.010 (0.25)

SEATING

–T–

PLANE

ISSUE E

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC

NOTES:

M 0 15 0 15 N 0.51 1.010.020 0.040

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

INCHESMILLIMETERS

____

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

Page 6

MC74HCT573A

–T–

U0.15 (0.006) T

L/2

PIN 1 IDENT

U0.15 (0.006) T

0.100 (0.004)

SEATING PLANE

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

20X REFK

0.10 (0.004) V

110

–V–

1120

JJ1

–U–

SECTION N–N

0.25 (0.010)

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHES

6.60 0.260

–W–

MILLIMETERS

DIMAMIN MAX MIN MAX

6.40 0.252

B 4.30 4.50 0.169 0.177 C 1.20 0.047

––– –––

D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: RMF AX0@email.sps.mot.com – T OUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET .com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MOTOROLA High–Speed CMOS Logic Data

*MC74HCT573A/D*

◊

MC74HCT573A/D

DL129 — Rev 6

Datasheet MC145017P, MC74HCT573ADT, MC74HCT573ADW Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual