Datasheet MC14490P, MC14490DW, MC14490L Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

297

MC14490

   

The MC14490 is constructed with complementary MOS enhancement mode devices, and is used for the elimination of extraneous level changes that result when interfacing with mechanical contacts. The digital contact bounce eliminator circuit takes an input signal from a bouncing contact and generates a clean digital signal four clock periods after the i nput has stabilized. The bounce eliminator circuit will remove bounce on both the “make” and the “break” of a contact closure. The clock for operation of the MC14490 is derived from an internal R–C oscillator which requires only an external capacitor to adjust for the desired operating frequency (bounce delay). The clock may also be driven from an external clock source or the oscillator of another MC14490 (see Figure 5).

NOTE: Immediately after power–up, the outputs of the MC14490 are in indeterminate states.

• Diode Protection on All Inputs

• Six Debouncers Per Package

• Internal Pullups on All Data Inputs

• Can Be Used as a Digital Integrator, System Synchronizer, or Delay

Line

• Internal Oscillator (R–C), or External Clock Source

• TTL Compatible Data Inputs/Outputs

• Single Line Input, Debounces Both “Make” and “Break” Contacts

• Does Not Require “Form C” (Single Pole Double Throw) Input Signal

• Cascadable for Longer Time Delays

• Schmitt Trigger on Clock Input (Pin 7)

• Supply Voltage Range = 3.0 V to 18 V

• Chip Complexity: 546 FETs or 136.5 Equivalent Gates

BLOCK DIAGRAM

Ain1

OSCin7

OSC

out

9

Bin14

Cin3

Din12

Ein5

Fin10

+V

DD

φ

1

φ

2

OSCILLATOR

AND

TWO–PHASE

CLOCK GENERATOR

DATA

SHIFT LOAD

4–BIT STATIC SHIFT REGISTER

1/2–BIT

DELAY

φ1φ

2

φ1φ

2

15 A

out

VDD = PIN 16

VSS = PIN 8

φ1φ

2

φ1φ

2

φ1φ

2

φ1φ

2

φ1φ

2

2 B

out

13 C

out

4 D

out

11 E

out

6 F

out

IDENTICAL TO ABOVE STAGE



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC

CASE 620

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

ORDERING INFORMATION

MC14490P Plastic MC14490L Ceramic MC14490DW SOIC

TA = – 55° to 125°C for all packages.

MOTOROLA CMOS LOGIC DATAMC14490

298

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

I

in

Input Current (DC or Transient), per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 MW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C to 125_C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

V

IL

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

(VO = 0.5 or 4.5 Vdc)

“1 Level” (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

V

IH

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

Oscillator Output Source

(VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V)

I

OH

5.0

5.0 10 15

– 0.6 – 0.12 – 0.23

– 1.4

— — — —

– 0.5 – 0.1 – 0.2 – 1.2

– 1.5 – 0.3 – 0.8 – 3.0

— — — —

– 0.4 – 0.08 – 0.16

– 1.0

ÎÎÎ

— — — —

mAdc

Debounce Outputs

(VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V)

5.0

5.0 10 15

– 0.9

– 0.19

– 0.6

1.8

— — — —

– 0.75 – 0.16

– 0.5 – 1.5

– 2.2

– 0.46

– 1.2 – 4.5

— — — —

– 0.6

– 0.12

– 0.4 – 1.2

ÎÎÎ

— — — —

Oscillator Output Sink

(VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V)

I

OL

5.0 10 15

0.36

0.9

4.2

— — —

0.3

0.75

3.5

0.9

2.3 10

— — —

0.24

0.6

2.8

ÎÎÎ

— — —

mAdc

Debounce Outputs

(VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V)

5.0 10 15

2.6

4.0 12

— — —

2.2

3.3 10

4.0

9.0 35

— — —

1.8

2.7

8.1

ÎÎÎ

— — —

Input Current

Debounce Inputs (Vin = VDD)

I

IH

15

—

2.0

—

0.2

2.0

—

ÎÎÎ

11

µAdc

Input Current Oscillator — Pin 7

(Vin = VSS or VDD)

I

in

15

—

± 620

—

± 255

± 400

—

ÎÎÎ

± 250

µAdc

Pullup Resistor Source Current

Debounce Inputs (Vin = VSS)

I

IL

5.0 10 15

175 340 505

375 740

1100

140 280 415

190 380 570

255 500 750

70 145 215

ÎÎÎ

225 440 660

µAdc

Input Capacitance

C

in

—

5.0

7.5

—

ÎÎÎ

—

pF

Quiescent Current

(Vin = VSS or VDD, I

out

= 0 µA)

I

SS

5.0 10 15

— — —

150 280 840

— — —

40 90

225

100 225 650

— — —

ÎÎÎ

90 180 550

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D

in

C

out

B

in

V

DD

OSC

out

F

in

E

out

D

out

C

in

B

out

A

in

V

SS

OSC

in

F

out

E

in

A

out

MOTOROLA CMOS LOGIC DATA

299

MC14490

SWITCHING CHARACTERISTICS (C

L

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise Time

All Outputs

ÎÎÎÎ

t

TLH

5.0 10 15

ÎÎÎÎ

— — —

180

90 65

360 180 130

ns

Output Fall Time Oscillator Output

ÎÎÎÎ

t

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

80

ns

Debounce Outputs

ÎÎÎÎ

t

THL

5.0 10 15

ÎÎÎÎ

— — —

60 30 20

120

60 40

Propagation Delay Time

Oscillator Input to Debounce Outputs

ÎÎÎÎ

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

285 120

95

570 240 190

ns

ÎÎÎÎ

t

PLH

5.0 10 15

ÎÎÎÎ

— — —

370 160 120

740 320 240

Clock Frequency (50% Duly Cycle)

(External Clock)

ÎÎÎÎ

f

cl

5.0 10 15

ÎÎÎÎ

— — —

2.8 6 9

1.4

3.0

4.5

MHz

Setup Time (See Figure 1)

ÎÎÎÎ

t

su

5.0 10 15

ÎÎÎÎ

100

80 60

50 40 30

— — —

ns

Maximum External Clock Input

Rise and Fall Time Oscillator Input

ÎÎÎÎ

tr, t

f

5.0 10 15

ОООООООООО

No Limit

ns

Oscillator Frequency

OSC

out

C

ext

≥ 100 pF*

Note: These equations are intended to be a design guide.

Laboratory experimentation may be required. Formulas are typically ± 15% of actual frequencies.

ÎÎÎÎ

f

osc

, typ

5.0

10

15

ОООООООООО

Hz

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

*POWER–DOWN CONSIDERATIONS

Large values of C

ext

may cause problems when powering down the MC14490 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the turn–off time of the power supply must not be faster than t = (VDD – VSS)  C

ext

/(10 mA). For example, If VDD – VSS = 15 V and

C

ext

= 1 µF, the power supply must turn off no faster than t = (15 V)  (1 µF)/10 mA = 1.5 ms. This is usually not a problem

because power supplies are heavily filtered and cannot discharge at this rate.

When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. T o avoid this possi-

bility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.

Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down

OSC

in

A

out

A

out

OSC

in

A

in

V

DD

0 V

V

DD

0 V V

DD

0 V

50%

90%

50%

10%

t

r

t

f

t

PHL

90%

10%

50%

t

su

50%

D1 D2C

ext

9

7

OSC

in

OSC

out

MC14490

t

PLH

V

DD

V

DD

1.5

C

ext

(in µF)

4.5

C

ext

(in µF)

6.5

C

ext

(in µF)

MOTOROLA CMOS LOGIC DATAMC14490

300

THEORY OF OPERATION

The MC14490 Hex Contact Bounce Eliminator is basically a digital integrator. The circuit can integrate both up a nd down. This enables the circuit to eliminate bounce on both the leading and trailing edges of the signal, shown in the timing diagram of Figure 3.

Each of the s ix Bounce E liminators i s composed of a 4–1/2–bit register (the integrator) and logic to compare the input with the contents of the shift register, as shown in Figure 4. The shift register requires a series of timing pulses in order to shift the input signal into each shift register location. These timing pulses (the clock signal) are represented in the upper waveform of Figure 3. Each of the six Bounce Eliminator circuits has an internal resistor as shown in Figure 4. A pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such as those coming from relay contacts and push buttons. By switching ground, rather than a power supply lead, system faults (such as shorts to ground on the signal input leads) will not cause excessive currents in the wiring and contacts. Signal lead shorts to ground a re much m ore probable t han shorts to a power supply lead.

When the relay contact is closed, (see Figure 4) the low level is inverted, and the shift register is loaded with a high on each positive edge of the clock signal. To understand the operation, we assume all bits of the shift register are loaded with lows and the output is at a high level.

At clock edge 1 (Figure 3) the input has gone low and a high has been loaded into the first bit or storage location of the shift register. Just after the positive edge of clock 1, the input signal has bounced back to a high. This causes the shift register to be reset to lows in all four bits — thus starting the timing sequence over again.

During clock edges 3 to 6 the input signal has stayed low. Thus, a high has been shifted into all four shift register bits and, as shown, the output goes low during the positive edge of clock pulse 6.

It should be noted that there is a 3–1/2 to 4–1/2 clock period delay between the clean input signal and output signal. In this example there is a delay of 3.8 clock periods from the beginning of the clean input signal.

After some time period of N clock periods, the contact is opened and at N+1 a low is loaded into the first bit. Just after N+1, when the input bounces low, all bits are set to a high. At N+2 nothing happens because the input and output are low and all bits of the shift register are high. At time N +3 and thereafter the input signal is a high, clean signal. At the positive edge of N+6 the output goes high as a result of four lows being shifted into the shift register.

Assuming the input signal is long enough to be clocked through the Bounce Eliminator, the output signal will be no longer or shorter than the clean input signal plus or minus one clock period.

The amount of time distortion between the input and output signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency. Since most relay contacts have more bounce when making as compared to breaking, the overall delay, counting bounce period, will be greater on the leading edge of the input signal than on the trailing edge. Thus, the output signal will be shorter than the input signal — if the leading edge bounce is included in the overall timing calculation.

The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at the beginning of the input signal. The input signal goes low three times before it finally settles down to a valid low state. The first three low pulses are referred to as false states.

If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). However, if an external clock is not available the user can place a small capacitor across the oscillator input and output pins in order to start up an internal clock source (as shown in Figure 4). The clock signal at the oscillator output pin may then be used to clock other MC14490 Bounce Eliminator packages. With the use of the MC14490, a large number of signals can be cleaned up, with the requirement of only one small capacitor external to the Hex Bounce Eliminator packages.

Figure 3. Timing Diagram

OSCin OR OSC

out

INPUT

OUTPUT

CONTACT

OPEN

CONTACT

BOUNCING

CONTACT CLOSED

(VALID TRUE SIGNAL)

CONTACT

BOUNCING

CONTACT OPEN

N + 7N + 5N + 3N + 1654321

MOTOROLA CMOS LOGIC DATA

301

MC14490

Figure 4. Typical “Form A” Contact Debounce Circuit

(Only One Debouncer Shown)

1/2 BIT DELAY

OSCILLATOR

AND

TWO–PHASE

CLOCK GENERATOR

C

ext

OSC

out

OSC

in

“FORM A”

CONTACT

A

in

1

9

7

φ

1

φ

2

DATA

SHIFT LOAD

4–BIT STATIC SHIFT REGISTER

φ1φ

2

φ1φ

2

15

A

out

+V

DD

PULLUP RESISTOR

(INTERNAL)

OPERATING CHARACTERISTICS

The single most important characteristic of the MC14490 is that it works with a single signal lead as an input, making it directly compatible with mechanical contacts (Form A and B).

The circuit has a built–in pullup resistor on each input. The worst case value of the pullup resistor (determined from the Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an external resistor may be connected between VDD and the input.

Because of the built–in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V. At this voltage, the input should be driven with paral-

leled s tandard g ates o r by the M C14049 o r MC14050 buffers.

The clock input circuit (pin 7) has Schmitt trigger shaping such that proper clocking will occur even with very slow clock edges, eliminating any need for clock preshaping. In addition, other MC14490 oscillator inputs can be driven from a single oscillator output buffered by an MC14050 (see Figure 5). Up to six MC14490s may be driven by a single buffer.

The MC14490 is TTL compatible on both the inputs and the outputs. When VDD is at 4.5 V, the buffered outputs can sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a result of the internal input pullup resistors.

Figure 5. Typical Single Oscillator Debounce System

FROM CONTACTS MC14490

TO SYSTEM

LOGIC

OSC

in

OSC

out

C

ext

1/6 MC14050

97

OSCin7 9 OSC

out

NO CONNECTION

FROM

CONTACTS

TO SYSTEM

LOGIC

MC14490

NO CONNECTION

9 OSC

out

OSCin7

FROM CONTACTS MC14490

TO SYSTEM

LOGIC

MOTOROLA CMOS LOGIC DATAMC14490

302

TYPICAL APPLICATIONS

ASYMMETRICAL TIMING

In applications where different leading and trailing edge delays are r equired (such as a fast a ttack/slow r elease timer.) Clocks of different frequencies can be gated into the MC14490 as shown in Figure 6. In order to produce a slow attack/fast release circuit leads A and B should be interchanged. The clock out lead can then be used to feed clock signals to the other MC14490 packages where the asymmetrical input/output timing is required.

Figure 6. Fast Attack/Slow Release Circuit

IN OUT

OSC

out

MC14011B

OSC

in

A B

f

C/N

EXTERNAL

CLOCK

÷

N

f

C

MC14490

LATCHED OUTPUT

The contents of the Bounce Eliminator can be latched by using several extra gates as shown in Figure 7. If the latch lead is high the clock will be stopped when the output goes low. This will hold the output low even though the input has returned to the high state. Any time the clock is stopped the outputs will be representative of the input signal four clock periods earlier.

Figure 7. Latched Output Circuit

IN OUT

OSC

out

MC14011B

OSC

in

MC14490

CLOCK

LATCH = 1

UNLATCH = 0

MULTIPLE TIMING SIGNALS

As shown in Figure 8, the Bounce Eliminator circuits can be connected in series. In this configuration each output is delayed by four clock periods relative to its respective input. This configuration may be used to generate multiple timing signals such as a delay line, for programming other timing operations.

One application of the above is shown in Figure 9, where it is required to have a single pulse output for a single operation (make) of the push button or relay contact. This only requires the series connection of two Bounce Eliminator circuits, one inverter, and one NOR gate in order to generate the signal A

B as shown in Figures 9 and 10. The signal AB is four clock periods in length. If the inverter is switched to the A output, the pulse AB will be generated upon release or break of the contact. With the use of a few additional parts many different pulses and waveshapes may be generated.

Figure 8. Multiple Timing Circuit Connections

10

5

12

3

14

1

7 9

6

11

4

13

2

15

A

out

B

out

C

out

D

out

E

out

F

out

OSC

in

CLOCK

B.E. 6

B.E. 5

B.E. 4

B.E. 3

B.E. 2

B.E. 1

OSC

out

A

in

B

in

C

in

D

in

E

in

F

in

MOTOROLA CMOS LOGIC DATA

303

MC14490

Figure 9. Single Pulse Output Circuit

IN

A

OUT

B

A

B

AB

A ≡ ACTIVE LOW B

≡

ACTIVE LOW

BE 2

BE 1

Figure 10. Multiple Output Signal Timing Diagram

OSCin OR

OSC

out

INPUT

A

B

C

D

E

F

A

B

AB

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATAMC14490

304

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50

E 0.050 BSC 1.27 BSC

F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31

L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

305

MC14490

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019

F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

M

B

M

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

–A–

–B– P8X

G14X

D16X

SEATING PLANE

–T–

S

A

M

0.010 (0.25) B

S

T

16 9

81

F

J

R

X 45

_

_ _ _ _

M

C

K

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MC14490/D

*MC14490/D*

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Datasheet MC14490P, MC14490DW, MC14490L Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual