Page 1
MC14489MOTOROLA
1
CMOS
The MC14489 is a f lexible l ight–emitting–diode d river which d irectly
interfaces to individual lamps, 7–segment displays, or various combinations of
both. LEDs wired with common cathodes are driven in a multiplexed–by–5
fashion. Communication with an MCU/MPU is established through a synchronous serial port. The MC14489 features data retention plus decode and scan
circuitry, thus relieving processor overhead. A single, current–setting resistor is
the only ancillary component required.
A single device can drive any one of the following: a 5–digit display plus
decimals, a 4–1/2–digit display plus decimals and sign, or 25 lamps. A special
technique allows driving 5 1/2 digits; see Figure 16. A configuration register
allows t he drive capability t o be partitioned off t o suit many a dditional
applications. The on–chip decoder outputs 7–segment–format numerals 0 to 9,
hexadecimal characters A to F, plus 15 letters and symbols.
The MC14489 is compatible with the Motorola SPI and National MICROWIRE serial data ports. The chip’s patented BitGrabber registers augment
the serial interface by allowing random access without steering or address bits.
A 24–bit transfer updates the display register. Changing the configuration
register requires an 8–bit transfer.
• Operating Voltage Range of Drive Circuitry: 4.5 to 6 V
• Operating Junction Temperature Range: – 40° to 130°C
• Current Sources Controlled by Single Resistor Provide Anode Drive
• Low–Resistance FET Switches Provide Direct Common Cathode Interface
• Low–Power Mode (Extinguishes the LEDs) and Brightness Controlled via
Serial Port
• Special Circuitry Minimizes EMI when Display is Driven and Eliminates
EMI in Low–Power Mode
• Power–On Reset (POR) Blanks the Display on Power–Up, Independent of
Supply Ramp Up Time
• May Be Used with Double–Heterojunction LEDs for Optimum Efficiency
• Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.)
• See Application Note AN431,
Temperature Measurement and Display
Using the MC68HC05B4 and the MC14489
and Engineering Bulletin
EB153,
Driving a Seven–Segment Display with the N
EURON
C
HIP
BitGrabber is a trademark of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Order this document
by MC14489/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
P SUFFIX
PLASTIC DIP
CASE 738
DW SUFFIX
SOG PACKAGE
CASE 751D
ORDERING INFORMATION
MC14489P Plastic DIP
MC14489DW SOG Package
b
d
V
DD
e
f
ENABLE
BANK 1
Rx
a
c 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
BANK 4
BANK 5
DATA OUT
h
g
CLOCK
DATA IN
BANK 2
V
SS
BANK 3
20
1
20
1
Motorola, Inc. 1995
REV 3
10/95
Page 2
MC14489 MOTOROLA
2
BLOCK DIAGRAM
1
BitGrabber
CONFIGURATION REGISTER
8 BITS
Rx
DATA OUT
8
2 20
12
BitGrabber
DISPLAY REGISTER
24 BITS
NIBBLE MUX AND
DECODER ROM
ANODE DRIVERS
(CURRENT SOURCES)
BANK SWITCHES (FETs)
194567
a b
DATA IN
c d e f g h
24–1/2–STAGE
SHIFT REGISTER
11
10
7
4
444
44
4
44444
18
POR
9 13 15 16 17
5
5
CLOCK
ENABLE
OSCILLATOR AND
CONTROL LOGIC
BANK 1 BANK 2 BANK 3 BANK 4 BANK 5
PIN 3 = V
DD
PIN 14 = V
SS
h DIM/BRIGHT
BLANK
a TO g
D
C
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 6.0
V
V
in
DC Input Voltage
– 0.5 to VDD + 0.5
V
V
out
DC Output Voltage
– 0.5 to VDD + 0.5
V
I
in
DC Input Current — per Pin
(Includes Pin 8)
± 15
mA
I
out
DC Output Current —
Pins 1, 2, 4 – 7, 19, 20 Sourcing
Sinking
– 40
10
mA
Pins 9, 13, 15, 16, 17 Sinking
320
Pin 18
± 15
IDD, ISSDC Supply Current, VDD and VSS Pins
± 350
mA
T
J
Chip Junction Temperature
– 40 to + 130
°C
R
θJA
Device Thermal Resistance,
Junction–to–Ambient (see Thermal
Considerations section) Plastic DIP
SOG Package
90
100
°C/W
T
stg
Storage Temperature
– 65 to + 150
°C
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
260
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and V
out
should be constrained to the range
VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
Page 3
MC14489MOTOROLA
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
, TJ = – 40° to 130°C* unless otherwise indicated)
Symbol
Parameter Test Condition
V
DD
V
Guaranteed
Limit
Unit
V
DD
Power Supply Voltage Range of LED Drive Circuitry — 4.5 to 6.0 V
VDD (stby) Minimum Standby Voltage Bits Retained in Display and
Configuration Registers, Data
Port Fully Functional
— 3.0 V
V
IL
Maximum Low–Level Input Voltage
(Data In, Clock, Enable
)
3.0
6.0
0.9
1.8
V
V
IH
Minimum High–Level Input Voltage
(Data In, Clock, Enable
)
3.0
6.0
2.1
4.2
V
V
Hys
Minimum Hysteresis Voltage
(Data In, Clock, Enable
)
3.0
6.0
0.2
0.4
V
V
OL
Maximum Low–Level Output Voltage
(Data Out)
I
out
= 20 µA 3.0
6.0
0.1
0.1
V
I
out
= 1.3 mA 4.5 0.4
V
OH
Minimum High–Level Output Voltage
(Data Out)
I
out
= – 20 µA 3.0
6.0
2.9
5.9
V
I
out
= – 800 µA 4.5 4.1
I
in
Maximum Input Leakage Current
Vin = VDD or V
SS
6.0 ± 2.0
µA
(Data In, Clock, Enable)
Vin = VDD or VSS,
TJ = 25°C only
6.0 ± 0.1
i
OL
Minimum Sinking Current
(a, b, c, d, e, f, g, h)
V
out
= 1.0 V 4.5 0.2 mA
i
OH
Peak Sourcing Current — See Figure 9 for currents up to
35 mA (a, b, c, d, e, f, g, h)
Rx = 2.0 kΩ, V
out
= 3.0 V,
Dimmer Bit = High
5.0 13 to 17.5
mA
Rx = 2.0 kΩ, V
out
= 3.0 V,
Dimmer Bit = Low
5.0 6 to 9
I
OZ
Maximum Output Leakage Current
V
out
= VDD (FET Leakage) 6.0 50
µA
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
V
out
= VDD (FET Leakage),
TJ = 25°C only
6.0 1
V
out
= VSS (Protection Diode
Leakage)
6.0 1
R
on
Maximum ON Resistance
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
I
out
= 0 to 200 mA 5.0 10 Ω
IDD, I
SS
Maximum Quiescent Supply Current
Device in Low–Power Mode,
Vin = VSS or VDD, Rx in
Place, Outputs Open
6.0 100
µA
Same as Above, TJ = 25°C 6.0 20
I
ss
Maximum RMS Operating Supply Current
(The VSS leg does not contain the Rx current component.
See Pin Descriptions.)
Device NOT in Low–Power
Mode, Vin = VSS or VDD,
Outputs Open
6.0 1.5 mA
*See Thermal Considerations section.
Page 4
MC14489 MOTOROLA
4
AC ELECTRICAL CHARACTERISTICS (T
J
= – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns)
Symbol
Parameter
V
DD
V
Guaranteed
Limit
Unit
f
clk
Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock tw below
(Figure 1)
3.0
4.5
6.0
dc to 3.0
dc to 4.0
dc to 4.0
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5)
3.0
4.5
6.0
140
80
80
ns
t
TLH
,
t
THL
Maximum Output Transistion Time, Data Out
(Figures 1 and 5)
3.0
4.5
6.0
70
50
50
ns
f
R
Refresh Rate — Bank 1 through Bank 5
(Figures 2 and 6)
3.0
4.5
6.0
NA
700 to 1900
700 to 1900
Hz
C
in
Maximum Input Capacitance — Data In, Clock, Enable — 10 pF
*See Thermal Considerations section.
TIMING REQUIREMENTS (T
J
= – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated)
Symbol Parameter
V
DD
V
Guaranteed
Limit
Unit
tsu, t
h
Minimum Setup and Hold Times, Data In versus Clock
(Figure 3)
3.0
4.5
6.0
50
40
40
ns
tsu, th,
t
rec
Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4)
3.0
4.5
6.0
150
100
100
ns
t
w(L)
Minimum Active–Low Pulse Width, Enable
(Figure 4)
3.0
4.5
6.0
4.5
3.4
3.4
µs
t
w(H)
Minimum Inactive–High Pulse Width, Enable
(Figure 4)
3.0
4.5
6.0
300
150
150
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
3.0
4.5
6.0
167
125
125
ns
tr, t
f
Maximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1)
3.0
4.5
6.0
1
1
1
ms
*See Thermal Considerations section.
**For a high–speed 8–Clock access, th for Enable
is determined as follows:
VDD = 3 to 4.5 V, f
clk
> 1.78 MHz: th = 4350 – (7500/f
clk
)
VDD = 4.5 to 6 V, f
clk
> 2.34 MHz: th = 3300 – (7500/f
clk
)
where th is in ns and f
clk
is in MHz.
NOTES:
1. This restriction does NOT apply for f
clk
rates less than those listed above. For “slow” f
clk
rates, use the th limits in the above table.
2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
Page 5
MC14489MOTOROLA
5
Figure 1. Figure 2.
10%
V
DD
1/f
clk
DATA OUT
CLOCK
90%
50%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
t
w
t
f
t
r
BANK
OUTPUT
50%
1/f
R
V
SS
Figure 3. Figure 4.
D
ATA IN
CLOCK
50%
VALID
50%
t
su
t
h
V
DD
V
DD
CLOCK
ENABLE
50%
t
su
t
h
FIRST
CLOCK
LAST
CLOCK
t
rec
50%
V
DD
V
DD
tw(H)
tw(L)
V
SS
V
SS
V
SS
V
SS
Figure 5. Figure 6.
TEST POINT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and fixture capacitance.
TEST POINT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and fixture capacitance.
V
DD
56
Ω
Page 6
MC14489 MOTOROLA
6
PIN DESCRIPTIONS
DIGITAL INTERFACE
Data In (Pin 12)
Serial Data Input. The bit stream begins with the MSB and
is shifted in on the low–to–high transition of Clock. When the
device is not cascaded, the bit pattern is either 1 byte (8 bits)
long to change the configuration register or 3 bytes (24 bits)
long to update the display register. For two chips cascaded,
the pattern is either 4 or 6 bytes, respectively. The display
does not change during shifting (until Enable
makes a low–
to–high transition) which allows slow serial data rates, if desired.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the two registers. Random access of either register is provided. That is, the registers may be accessed in any sequence. Data is retained in
the registers over a supply range of 3 to 6 V. The format is
shown in Figures 7 and 8. Information on the segment decoder is given in Table 1.
Data In typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. These features combine to
maximize noise immunity for use in harsh environments and
bus applications. T his input can b e directly interfaced to
CMOS devices with outputs guaranteed to switch near rail–
to–rail. When interfacing to NMOS or TTL devices, either a
level shifter (MC14504B, MC74HCT04A) or pullup resistor of
1 kΩ to 10 kΩ must be used. Parameters to be considered
when sizing the resistor are the worst–case IOL of the driving
device, maximum tolerable power consumption, and maximum data rate.
Clock (Pin 11)
Serial Data Clock Input. Low–to–high transitions on Clock
shift bits available at Data In, while high–to–low transitions
shift bits from Data Out. The chip’s 24–1/2–stage shift register is static, allowing clock rates down to dc in a continuous
or intermittent mode. The Clock input does not need to be
synchronous with the on–chip clock oscillator which drives
the multiplexing circuit.
Eight clock cycles are required to access the configuration
register, while 24 are needed for the display register when
the MC14489 is not cascaded. See Figures 7 and 10.
As shown in Figure 11, two devices may be cascaded. In
this case, 32 clock cycles access the configuration register
and 48 access the display register, as depicted in Figure 8.
Cascading of 3, 4, and 5 devices is shown in Figures 12,
13, and 14, respectively.
Clock typically switches near 50% o f VDD and h as a
Schmitt–triggered input buffer. Slow Clock rise and fall times
are tolerated. See the last paragraph of Data In for more information.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the Clock pin must NOT be
floated or toggled during power–up. That is, the
Clock pin m ust b e stable until the VDD pin
reaches at least 3 V.
If control of the Clock pin during power–up is not
practical, then the MC14489 must be reset via bit
C0 in the C register. To accomplish this, C0 is reset low, then set high.
Enable
(Pin 10)
Active–Low Enable Input. This pin allows the MC14489 to
be used on a serial bus, sharing Data In and Clock with other
peripherals. When Enable
is in an inactive high state, Data
Out is forced to a known (low) state, shifting is inhibited, and
the port is held in the initialized state. To transfer data to the
device, Enable
(which initially must be inactive high) is taken
low, a serial transfer is made via Data In and Clock, and
Enable is taken high. The low–to–high transition on Enable
transfers data to either the configuration or display register,
depending on the data stream length.
Every rising edge on Enable initiates a blanking interval
while data is loaded. Thus, continually loading the device
with the same data may cause the LEDs on some banks to
appear dimmer than others.
NOTE
Transitions on Enable
must not be attempted
while Clock is high. This puts the device out of
synchronization with the microcontroller. Resynchronization occurs when Enable
is high a nd
Clock is low.
This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading erroneous data in the registers. See the last paragraph of Data In
for more information.
Data Out (Pin 18)
Serial Data Output. Data is transferred out of the shift register through Data Out on the high–to–low transition of Clock.
This output is a no connect, unless used in one of the manners discussed below.
When cascading MC14489’s, Data Out feeds Data In of
the next device per Figures 11, 12, 13, and 14.
Data Out could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a system check conducted at power–up to test the integrity of the
system’s processor, pc board traces, solder joints, etc.
The pin could be monitored at an in–line Q.A. test during
board manufacturing.
Finally, Data Out facilitates troubleshooting a system.
DISPLAY INTERFACE
Rx (Pin 8)
External Current–Setting Resistor. A resistor tied between
this pin and ground (VSS) determines the peak segment drive
current delivered at pins a through h. Pin 8’s resistor ties into
a current mirror with an approximate current gain of 10 when
bit D23 = high (brighten). With D23 = low, the peak current is
reduced about 50%. Values for Rx range from 700 Ω to infin-
ity. When Rx = ∞ (open circuit), the display is extinguished.
For proper current control, resistors having ± 1% tolerance
should be used. See Figure 9.
CAUTION
Small Rx values may cause the chip to overheat
if precautions are not observed. See Thermal
Considerations.
Page 7
MC14489MOTOROLA
7
a through h (Pins 1, 2, 4 – 7, 19, 20)
Anode–Driver Current Sources. These outputs are closely–matched current sources which directly tie to the anodes
of external discrete LEDs (lamps) or display segment LEDs.
Each output is capable of sourcing up to 35 mA.
When used with lamps, outputs a, b, c, and d are used to
independently control up to 20 lamps. Output h is used to
control up to 5 lamps dependently. (See Figure 17.) For
lamps, the
No Decode
mode is selected via the configuration
register, forcing e, f, and g inactive (low).
When used with segmented displays, outputs a through g
drive segments a through g, respectively . Output h is used to
drive the decimals. If unused, h must be left open. Refer to
Figure 10.
Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17)
Diode–Bank FET Switches. These outputs are low–resistance switches to ground (VSS) capable of handling currents
of up to 320 mA each. These pins directly tie to the common
cathodes of segmented displays or the cathodes of lamps
(wired with cathodes common).
The display is refreshed at a nominal 1 kHz rate to achieve
optimum brightness from the LEDs. A 20% duty cycle is utilized.
Special design techniques are used on–chip to accommodate the high currents with low EMI (electromagnetic interference) and minimal spiking on the power lines.
POWER SUPPLY
VSS (Pin 14)
Most–negative supply potential. This pin is usually ground.
Resistor Rx is externally tied to ground (VSS). Therefore,
the chip’s VSS pin does not contain the Rx current component.
VDD (Pin 13)
Most–positive supply potential.
To guarantee data integrity in the registers and to ensure
the serial interface is functional, this voltage may range from
3 to 6 volts with respect to VSS. For example, within this voltage range, the chip could be placed in and out of the low–
power mode.
To adequately drive the LEDs, this voltage must be 4.5 to
6 volts with respect to VSS.
The VDD pin contains the Rx current component plus the
chip’s current drain. In the low–power mode, the current mirror and clock oscillator are turned off, thus significantly reducing the VDD current, IDD.
Page 8
MC14489 MOTOROLA
8
Figure 7. Timing Diagrams for Non–Cascaded Devices
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D23
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 241
MSB LSB
L = DIM LEDs, H = BRIGHTEN LEDs
THE LSBs OF EACH BANK NIBBLE ARE D0, D4, D8, D12, AND D16.
BANK 5
NOTE: The low–power (standby) mode places the device
C6 C5 C4 C3 C2 C1C7
2 3 4 5 6 7 81
MSB
ENABLE
CLOCK
DATA IN
in a static state, thus eliminating EMI and mux switching
noise. Therefore, during precision analog measurements,
the low–power mode could be invoked by a system’s MCU.
Also, the low–power mode blanks the display, and could
be used to flash the LEDs on and off.
C0
L = LOW POWER MODE (BLANKS THE DISPLAY), FORCED LOW (L) BY POWER ON RESET
H = NORMAL MODE
CONTROLS BANK 1:
CONTROLS BANK 2: L = HEX DECODE, H = DEPENDS ON C6
CONTROLS BANK 3: L = HEX DECODE, H = DEPENDS ON C6
CONTROLS BANK 4: L = HEX DECODE, H = DEPENDS ON C7
CONTROLS BANK 5: L = HEX DECODE, H = DEPENDS ON C7
SEE TABLE 1
L = NO DECODE, H = SPECIAL DECODE (REFER TO C1, C2, AND C3)
L = NO DECODE, H = SPECIAL DECODE (REFER TO C4 AND C5)
LLLLHHH
H
LLHHLLH
H
LHLHLHL
H
= ALL h OUTPUTS INACTIVE
= ACTIVATE h IN BANK 1
= ACTIVATE h IN BANK 2
= ACTIVATE h IN BANK 3
= ACTIVATE h IN BANK 4
= ACTIVATE h IN BANK 5
= ACTIVATE h IN BOTH BANKS 1 AND 2
= ACTIVATE h IN ALL BANKS
NIBBLE
BANK 4
NIBBLE
BANK 3
NIBBLE
BANK 2
NIBBLE
BANK 1
NIBBLE
SEE TABLE 1
ENABLE
CLCOK
DATA IN
LSB
(a) Configuration Register Format (1 Byte)
(b) Display Register Format (3 Bytes)
NOTE: L = Low Voltage Level (Logic 0), H = High Voltage Level (Logic 1)
L = HEX DECODE, H = DEPENDS ON C6
Page 9
MC14489MOTOROLA
9
Table 1. Triple–Mode Segment Decoder Function Table
Lamp Conditions
Bank Nibble Value
7–Segment Display
Characters
No Decode
(Invoked via
Bits C1 to C7)
Hexadecimal
Binary
MSB LSB
Hex Decode
(Invoked via
Bits C1 to C5)
Special
Decode
(Invoked via
Bits C1 to C7)
d c b a
$0
$1
$2
$3
L L L L
L L L H
L L H L
L L H H
on
on
on
on
$4
$5
$6
$7
L H L L
L H L H
L H H L
L H H H
on
on
on
on
on
on
on
on
$8
$9
$A
$B
H L L L
H L L H
H L H L
H L H H
on
on
on
on
on
on
on
on
$C
$D
$E
$F
H H L L
H H L H
H H H L
H H H H
on
on
on
on
on
on
on
on
on
on
on
on
NOTES:
1. In the
No Decode
mode, outputs e, f, and g are unused and are all forced inactive (low). Output
h decoding is unaffected, i.e., unchanged from the other modes. The
No Decode
mode is used
for three purposes:
a. Individually controlling lamps.
b. Controlling a half digit with sign.
c. Controlling annunciators - examples: AM, PM, UHF, kV, mm Hg.
2. Can be used as capital S.
3. Can be used as capital B.
4. Can be used as small g.
Page 10
MC14489 MOTOROLA
10
(a) Configuration Registers
C7 C6 C5 C4 C3 C2 C1 C0
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE
CONFIGURATION
REGISTER OF
DEVICE 2 IN
FIGURE 11
CONFIGURATION
REGISTER OF
DEVICE 1 IN
FIGURE 11
DON’T CARE DON’T CARE
(b) Display Registers
Figure 8. Bit Stream Formats for Two Devices Cascaded
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE
h BITS
AND
DIMMER
BIT
h BITS
AND
DIMMER
BIT
5TH BYTE
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
6TH BYTE
DISPLAY REGISTER OF DEVICE 2
IN FIGURE 11
DISPLAY REGISTER OF DEVICE 1
IN FIGURE 11
NOTE: ENABLE (which initially must be inactive high) is kept active–low during the entire 4–byte configuration transfer or 6–byte display
transfer. When ENABLE
is brought back high, either a 4– or 6–byte transfer occurs in the cascaded devices, depending on the number
of bytes in the transfer.
Figure 9. a through h Nominal Current per Output versus Rx
35
30
25
20
15
10
5
400 800 1.2 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k1.6 k
i
OH,
PEAK DRIVE CURRENT (mA)
5 V SUPPLY
BIT D23 = HIGH (BRIGHTEN LEDs)
WITH D23 = LOW, iOH IS CUT BY ∼50%.
Rx, EXTERNAL RESISTOR (Ω)
NOTE: Drive current tolerance is approximately ± 15%.
Page 11
MC14489MOTOROLA
11
APPLICATIONS INFORMATION
Figure 10. Non–Cascaded Application Example: 5 Character Common Cathode
LED Display with Two Intensities as Controlled via Serial Port
#5 #4 #3 #2 #1
8
8 8 8 8 8
d
a
b
ce
f
g
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
d
a
b
c
e
f
g
h
OPTIONAL
CMOS
MCU/MPU
+ 5 V
Rx
V
DD
V
SS
DATA OUT
Rx
DATA IN
CLOCK
ENABLE
+ 5 V
MC14489
•
Figure 11. Cascading Two Devices
OPTIONAL
CMOS
MCU/MPU
DATA
OUT
CLOCK ENABLE
MC14489 #1
DATA
IN
DATA
OUT
CLOCK ENABLE
MC14489 #2
DATA
IN
a TO h
BANK 1
TO
BANK 5
a TO h
BANK 1
TO
BANK 5
Page 12
MC14489 MOTOROLA
12
Figure 12. Bit Stream Formats for Three Devices Cascaded
a TO h
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
a TO h a TO h
MC14489 #1 MC14489 #2 MC14489 #3
DATA
IN CLOCK
DATA
OUT
DATA
IN CLOCK
DATA
OUT
DATA
IN CLOCK
DATA
OUT
OPTIONAL
C0C1C2C3C4C5C6C7
CMOS
MCU/MPU
DON’T CARE
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE 7TH BYTE
8TH (LAST)
BYTE
DON’T CARE DON’T CARE
DON’T CARE
DON’T CARE
CONFIGURATION
REGISTER OF
DEVICE #1
CONFIGURATION
REGISTER OF
DEVICE #2
CONFIGURATION
REGISTER OF
DEVICE #3
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE 7TH BYTE 8TH BYTE 9TH BYTE
10TH (LAST)
BYTE
DON’T
CARE
(OPTIONAL,
SEE NOTE)
DISPLAY REGISTER OF DEVICE #3 DISPLAY REGISTER OF DEVICE #2 DISPLAY REGISTER OF DEVICE #1
h BITS
AND
DIMMER
BIT
h BITS
AND
DIMMER
BIT
h BITS
AND
DIMMER
BIT
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
(a) Cascading Three Devices
(b) Configuration Registers
(c) Display Registers
ENABLEENABLEENABLE
NOTE: When the leading “don’t care” bytes are included, ENABLE (which initially must be inactive high) is kept active–low during the entire 8–byte configuration transfer or 10–byte display transfer.
When ENABLE is brought back high, either an 8– or 10–byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the one “don’t care” byte can be
eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t (H) spec, (4) transfer last 3 bytes, and (5) take ENABLE inactive high.
w
Page 13
MC14489MOTOROLA
13
Figure 13. Bit Stream Formats for Four Devices Cascaded
a TO h
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
a TO h a TO h
MC14489 #1 MC14489 #2 MC14489 #4
DATA
IN CLOCK
DATA
OUT
DATA
IN CLOCK
DATA
OUT
DATA
IN CLOCK
DATA
OUT
OPTIONAL
C0C1C2C3C4C5C6C7
CMOS
MCU/MPU
DON’T CARE
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE
5TH BYTE 6TH BYTE
7TH BYTE
8TH BYTE
DON’T CARE DON’T CARE DON’T CARE DON’T CARE
CONFIGURATION
REGISTER OF
DEVICE #3
CONFIGURATION
REGISTER OF
DEVICE #4
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE 7TH BYTE 8TH BYTE 13TH BYTE
14th (LAST)
BYTE
DON’T
CARE
(OPTIONAL,
SEE NOTE)
DISPLAY REGISTER OF DEVICE #4 DISPLAY REGISTER OF DEVICE #3 DISPLAY REGISTER OF DEVICE #1
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
1
NIBBLE
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
1
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
(a) Cascading Four Devices
(b) Configuration Registers
BANK 1
TO
BANK 5
a TO h
MC14489 #3
DATA
IN CLOCK
DATA
OUT
9TH BYTE 10TH BYTE 11TH BYTE
12TH (LAST)
BYTE
DON’T CARE DON’T CARE
CONFIGURATION
REGISTER OF
DEVICE #1
CONFIGURATION
REGISTER OF
DEVICE #2
12TH BYTE
h BITS
AND
DIMMER
BIT
BANK
5
NIBBLE
DON’T
CARE
(OPTIONAL,
SEE NOTE)
DON’T CARE
ENABLEENABLEENABLEENABLE
h BITS
AND
DIMMER
BIT
BANK
2
NIBBLE
h BITS
AND
DIMMER
BIT
BANK
2
NIBBLE
(c) Display Registers
NOTE: When the leading “don’t care” bytes are included, ENABLE (which initially must be inactive high) is kept active–low during the entire 12–byte configuration transfer or 14–byte display transfer.
When ENABLE is brought back high, either a 12– or 14–byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the two “don’t care” bytes can be
eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t (H) spec, (4) transfer last 6 bytes, and (5) take ENABLE inactive high.
w
Page 14
MC14489 MOTOROLA
14
Figure 14. Bit Stream Formats for Five Devices Cascaded
a TO h
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
BANK 1
TO
BANK 5
a TO h a TO h
MC14489 #1 MC14489 #2 MC14489 #5
DATA
IN CLOCK ENABLE
DATA
OUT
DATA
IN CLOCK ENABLE
DATA
OUT
DATA
IN CLOCK ENABLE
DATA
OUT
OPTIONAL
C0C1C2C3C4C5C6C7
CMOS
MCU/MPU
DON’T CARE
1ST BYTE
SHIFTED IN
2ND BYTE 3RD BYTE 4TH BYTE
5TH BYTE 6TH BYTE
7TH BYTE
8TH BYTE
DON’T CARE DON’T CARE DON’T CARE
CONFIGURATION
REGISTER OF
DEVICE #3
CONFIGURATION
REGISTER OF
DEVICE #5
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23
1ST BYTE
SHIFTED IN
2ND BYTE 4TH BYTE 5TH BYTE 6TH BYTE
14TH BYTE
15TH (LAST)
BYTE
DISPLAY REGISTER OF DEVICE #5 DISPLAY REGISTER OF DEVICE #4 DISPLAY REGISTER OF DEVICE #1
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
(a) Cascading Five Devices
NOTE: ENABLE (which initially must be inactive high) is kept active–low during the entire 13–byte configuration transfer or 15–byte display transfer. When
ENABLE is brought back high, either a 13– or 15–byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer.
BANK 1
TO
BANK 5
a TO h
MC14489 #3
DATA
IN CLOCK ENABLE
DATA
OUT
9TH BYTE 10TH BYTE 11TH BYTE
13TH (LAST)
BYTE
DON’T CARE DON’T CARE
CONFIGURATION
REGISTER OF
DEVICE #1
CONFIGURATION
REGISTER OF
DEVICE #2
13TH BYTE
h BITS
AND
DIMMER
BIT
BANK
5
NIBBLE
DON’T CARE
3RD BYTE
CONFIGURATION
REGISTER OF
DEVICE #4
12TH BYTE
DON’T CARE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
h BITS
AND
DIMMER
BIT
BANK
5
NIBBLE
BANK
4
NIBBLE
BANK
3
NIBBLE
BANK
2
NIBBLE
BANK
1
NIBBLE
h BITS
AND
DIMMER
BIT
BANK
5
NIBBLE
(b) Configuration Registers
(c) Display Registers
Page 15
MC14489MOTOROLA
15
Figure 15. Common–Cathode LED Display with Dial–Adjusted Brightness
V
SS
CMOS
MCU/MPU
Rx
LED DISPLAY
MC14489
8 5
+ 5 V
R1
R2
V
DD
+ 5 V
NOTE: R1 limits the maximum current to avoid damaging the display and/or the MC14489
due to overheating. See the Thermal Considerations section. An 1/8 watt resistor
may be used for R1. R2 is a 1 kΩ or 5 kΩ potentiometer (≥ 1/8 watt). R2 may be a
light–sensitive resistor.
Figure 16. Driving 5 1/2 Digits
4
UNIVERSAL OVERFLOW
(“1” OR “HALF–DIGIT”)
MC14489
5h
3
a TO g
321
BANK OUTPUTS
7
USE TO DRIVE LAMP
OR MINUS SIGN
5–DIGIT DISPLAY
INPUT LINES
NOTE: A Universal Overflow pins out all anodes and cathodes.
Page 16
MC14489 MOTOROLA
16
Figure 17. 25–Lamp Application
3
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
d
a
b
c
e
f
g
h
CMOS
MCU/MPU
NC
NC
NC
MC14489
THESE LAMPS DEPENDENTLY
CONTROLLED WITH
BITS D20, D21, AND D22*
THESE LAMPS
INDEPENDENTLY
CONTROLLED WITH
BITS D0 TO D19
*If required, this group of lamps can be independently controlled. To accomplish independent control, only connect lamps to BANK 1 and
BANK 2 for output h (two lamps). Then, use bits D20, D21, and D22 for control of these two lamps.
Page 17
MC14489MOTOROLA
17
Figure 18. 4–Digit Display Plus Decimals with Four Annunciators
or 4–1/2–Digit Display Plus Sign
4
CMOS MCU/MPU
a TO d BANK 1
TO
BANK 4
BANK 5
MC14489
4 4
e TO h
3
4
•
Figure 19. Compact Display System with Three Components
INPUT LINES
3
8
14
MC14489
MUXED 5–DIGIT MONOLITHIC DISPLAY (CLUSTER)
HEWLETT–PACKARD 5082–7415 OR EQUIVALENT
12 3 6 2 10 8 5 1 13 4 9 7
6 5 4 2 1 20 19 17 16 15 13 97
Page 18
MC14489 MOTOROLA
18
THERMAL CONSIDERATIONS
The MC14489 is designed to operate with a
chip–junction
temperature (TJ) ranging from – 40 to 130°C, as indicated in
the electrical characteristics tables. The
ambient
operating
temperature range (TA) is dependent on R
θJA
, the internal
chip current, how many anode drivers are used, the number
of bank drivers used, the drive current, and how the package
is cooled. The maximum ratings table gives the thermal resistance, junction–to–ambient, of the MC14489 mounted on
a pc board using natural convection to be 90°C per watt for
the plastic DIP. The SOG thermal resistance is 100°C per
watt.
The following general equation (1) is used to determine the
power dissipated by the MC14489.
PT = PD + P
I
(1)
where
PT= Total power dissipation of the MC14489
PD= Power dissipated in the driver circuitry (mW)
PI= Power dissipated by the internal chip
circuitry (mW)
The equations for the two terms of the general equation
are:
PD = (iOH) (N)(VDD – V
LED
)(B/5) (2)
(3)PI = (1.5 mA)(VDD) + IRx(VDD – IRxRx)
where
iOH= Peak anode driver current (mA)
IRx= iOH /10, with iOH = the peak anode driver current
(mA) when the dimmer bit is high
N = Number of anode drivers used
B = Number of bank drivers used
Rx = External resistor value (kΩ)
VDD= Maximum supply voltage, referenced to V
SS
(volts)
V
LED
= Minimum anticipated voltage drop across the
LED
1.5 mA = Operating supply current of the MC14489
The following two examples show how to calculate the
maximum allowable ambient temperature.
Worst–Case Analysis Example 1:
5–digit display with decimals (5 banks and 8 anode drivers)
DIP without heat sink on PC board
iOH= 20 mA max
V
LED
= 1.8 V min
VDD= 5.25 max
PD = (20)(8)(5.25 – 1.8)(5/5) = 552 mW Ref. (2)
PI = (1.5)(5.25) + 2[5.25 – 2(2)] = 10 mW Ref. (3)
Therefore, PT = 552 + 10 = 562 mW Ref. (1)
and ∆T
chip
= R
θJAPT
= (90°C/W)(0.562) = 51°C
Finally, the maximum allowable
TA = TJmax – ∆T
chip
= 130 – 51 = 79°C
That is, if TA = 79°C, the maximum junction temperature is
130°C. The chip’s average temperature for this example is
lower than 130°C because all segments are usually not illuminated simultaneously for an indefinite period.
Worst–Case Analysis Example 2:
16 lamps (4 banks and 4 anode drivers)
SOG without heat sink on PC board
iOH= 30 mA max
V
LED
= 1.8 V min
VDD= 5.5 max
PD = (30)(4)(5.5 – 1.8)(4/5) = 355 mW Ref. (2)
PI = (1.5)(5.5) + 3[5.5 – 3(1.0)] = 16 mW Ref. (3)
Therefore, PT = 355 + 16 = 371 mW Ref. (1)
and ∆T
chip
= R
θJAPT
= (100°C/W)(0.371) = 37°C
Finally, the maximum allowable
TA = TJmax – ∆T
chip
= 130 – 37 = 93°C
To extend the allowable ambient temperature range or to
reduce TJ, which extends chip life, a heat sink s uch as
shown in Figure 20 can be used in high–current applications.
Alternatively, heat–spreader techniques can be used on the
PC board, such as running a wide trace under the MC14489
and using thermal paste. W ide, radial traces from the
MC14489 leads also act as heat spreaders.
AAVID #5804 or equivalent
(Tel. 603/524–4443, FAX 603/528–1478)
Motorola cannot recommend one supplier over another and
in no way suggests that this is the only heat sink supplier.
Figure 20. Heat Sink
Page 19
MC14489MOTOROLA
19
Table 2. LED Lamp and Common–Cathode
Display Manufacturers
Supplier Contact Information
QT Optoelectronics Phone: (800) 533–6786
FAX: (214) 447–0784
Hewlett–Packard (HP),
Components Group
Contact your local HP
Components Sales Office
Industrial Electronic
Engineers (IEE),
Component Products Div.
Phone: (818) 787–0311
FAX: (818) 901–9046
Purdy Electronics Corp.,
AND Product Line
Phone: (408) 523–8210
FAX: (408) 733–1287
NOTE: Motorola cannot recommend one supplier over another
and in no way suggests that this is a complete listing of
LED suppliers.
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 738–03
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15
°
0.040
1.010
0.240
0.150
0.015
0.050
0.008
0.110
0
°
0.020
25.66
6.10
3.81
0.39
1.27
0.21
2.80
0
°
0.51
27.17
6.60
4.57
0.55
1.77
0.38
3.55
15
°
1.01
0.050 BSC
0.100 BSC
0.300 BSC
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-A-
C
K
N
E
G F
D
20 PL
J 20 PL
L
M
-T-
SEATING
PLANE
1 10
1120
0.25 (0.010) T A
M M
0.25 (0.010) T B
M M
B
Page 20
MC14489 MOTOROLA
20
DW SUFFIX
SOG PACKAGE
CASE 751D–04
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
_ _
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MC14489/D
*MC14489/D*
◊
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