Datasheet MC14194BCL, MC14194BCP, MC14194BD Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATAMC14194B

284

    

The MC14194B is a 4–bit static shift register capable of operating in the parallel l oad, serial shift left, serial s hift right, or hold mode. The asynchronous Reset input, when at a low level, overrides all other inputs, resets all stages, and forces all outputs low. When Reset

is at a logic 1 level, the two mode control inputs, S0 and S1, control the operating mode as shown in the truth table. Both serial and parallel operation are triggered on the positive–going transition of the Clock input. The Parallel Data, Data Shift, and mode control inputs must be stable for the specified setup and hold times before and after the positive–going Clock transition.

• Synchronous Right/Left Serial Operation

• Synchronous Parallel Load

• Asynchronous Hold (Do Nothing) Mode

• Functional Pin for Pin Equivalent of LS194

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, I

out

Input or Output Current (DC or Transient), per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

Q

LOGIC DIAGRAM

RESET

CLOCK

DSR

S0

S1

1

11

2

9

10

5

643

D

P1

D

P0

D

P2

D

P3

7

DSL

Q0 Q1 Q2 Q3

15 14 13 12

D

R

D Q D Q D Q

C C C C

R R R

VDD = PIN 16

VSS = PIN 8



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATA

285

MC14194B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

“0” Level

Vin = VDD or 0

V

OL

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

V

IL

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

V

IH

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

I

OH

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

I

OL

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

5.0

7.5

—

ÎÎÎ

—

pF

Quiescent Current

(Per Package)

I

DD

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

I

T

5.0 10 15

IT = (0.95 µA/kHz) f + I

DD

IT = (1.90 µA/kHz) f + I

DD

IT = (2.90 µA/kHz) f + I

DD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q3

Q2

Q1

V

DD

S0

S1

C

D

P1

D

P0

DSR

R

V

SS

DSL

D

P3

D

P2

Q0

Output Voltage

Input Voltage

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

MOTOROLA CMOS LOGIC DATAMC14194B

286

TRUTH TABLE

Operating

Inputs

(Reset

= 1)

Outputs (@ t

n+1

)

Operating

Mode

S1 S0 DSR DSL D

P0–3

Q0 Q1 Q2 Q3

Hold 0 0 X X X Q0 Q1 Q2 Q3

1 0 X 0 X Q1 Q2 Q3 0

Shift Left

1 0 X 1 X Q1 Q2 Q3 1 0 1 0 X X 0 Q0 Q1 Q2

Shift Right

0 1 1 X X 1 Q0 Q1 Q2 1 1 X X 0 0 0 0 0

Parallel

1 1 X X 1 1 1 1 1

X = Don’t Care t

n+1

= State after the next positive–going transition of the clock.

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.35 ns/pF) CL + 32 ns

t

TLH

, t

THL

= (0.6 ns/pF) CL + 20 ns

t

TLH

, t

THL

= (0.4 ns/pF) CL + 20 ns

ÎÎÎÎ

t

TLH

, t

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

80

ns

ÎÎÎÎ

t

PLH,tPHL

5.0 10 15

ÎÎÎÎ

— — —

275

110

85

550 220 170

ns

to Q

t

PHL

= (0.9 ns/pF) CL + 305 ns

t

PHL

= (0.36 ns/pF) CL + 122 ns

t

PHL

= (0.26 ns/pF) CL + 97 ns

ÎÎÎÎ

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

350 140

110

700 280 220

ns

Clock Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

280 110

85

140

55 40

— — —

ns

Reset Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

180

70 50

90 35 26

— — —

ns

Clock Pulse Frequency

(Shift Right or Left Mode)

ÎÎÎÎ

f

cl

5.0 10 15

ÎÎÎÎ

— — —

3.6

9.0 12

1.8

4.5

6.0

MHz

Clock Pulse Rise and Fall Time

ÎÎÎÎ

t

TLH

, t

THL

5.0 10 15

ÎÎÎÎ

— — —

15

5 4

µs

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

10 20 40

– 8.0

0

9.0

— — —

ns

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

200

75 55

100

36 27

— — —

ns

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

180

50 35

90 25 10

— — —

ns

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

0 0 0

– 40 – 27 – 20

— — —

ns

Reset Removal Time

ÎÎÎÎ

t

rem

5.0 10 15

ÎÎÎÎ

300 110

80

150

55 40

— — —

ns

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Propagation Delay Time

Clock to Q

Reset

t

, t

PLH

t

PLH

t

PLH

= (0.9 ns/pF) CL + 230 ns

PHL

, t

= (0.36 ns/pF) CL + 92 ns

PHL

, t

= (0.26 ns/pF) CL + 72 ns

PHL

Setup Time

Data to Clock

t

su

Mode Control (S) to Clock

Hold Time

Data to Clock

t

h

Mode Control (S) to Clock

MOTOROLA CMOS LOGIC DATA

287

MC14194B

Figure 1. Switching Time Test Circuits and Waveforms

PULSE

GENERATOR

PULSE

GENERATOR

V

DD

V

DD

16 16

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

15

14

13

12

15

14

13

12

Q0

Q1

Q2

Q3

Q0

Q1

Q2

Q3

D

P0

D

P1

D

P2

D

P3

CLOCK DSR DSL S0 S1

3 4 5 6

11

2 7 9

10

1

8 V

SS

R

D

P0

D

P1

D

P2

D

P3

CLOCK DSR DSL S0 S1

R

8 V

SS

3 4 5 6

11

2 7 9

10

1

NOTE: Interchange DSR with DSL and S0 with

S1 for testing shift left.

20 ns 20 ns

90%

50%

10%

DPn

DSR

DSL

CLOCK

Q

n

RESET

t

h

t

su

t

su

t

h

50%

90%

50%

10%

t

TLH

t

THL

t

PLH

t

PHL

t

WH(cl)

1/f

cl

t

PHL

t

rem

t

WL

50%

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

V

DD

V

SS

Parallel Load Serial Load

Figure 2. Dynamic Power Dissipation Test Circuit and Waveforms

PULSE

GENERATOR

C

L

C

L

C

L

C

L

3 4 5 6

11

2 7 9

10

1

V

DD

16

D

P0

D

P1

D

P2

D

P3

CLOCK DSR DSL S0 S1

R

Q0

Q1

Q2

Q3

500

µ

FI

D

8 V

SS

15

14

13

12

20 ns 20 ns

50%

90%

DSR

CLOCK

Q

n

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

1/f

10%

MOTOROLA CMOS LOGIC DATAMC14194B

288

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

289

MC14194B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

_ _ _ _

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer .

MC14194B/D

*MC14194B/D*

◊