Datasheet MC14174BCP, MC14174BD, MC14174BDR2, MC14174BF, MC14174BFEL Datasheet (MOTOROLA)

MC14174B

Hex Type D Flip-Flop

The MC14174B hex type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the clock pulse. All six flip–flops share common clock and reset inputs. The reset is active low, and independent of the clock.

• Static Operation

• All Inputs and Outputs Buffered

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving T wo Low–Power TTL Loads or One Low–Power

Schottky TTL Load over the Rated T emperature Range

• Functional Equivalent to TTL 74174

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C Lead Temperature

L

SS

or VDD). Unused outputs must be left open.

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14174BCP

AWLYYWW

1

16

14174B

AWLYWW

1

16

MC14174B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14174BCP PDIP–16 2000/Box MC14174BD SOIC–16 48/Rail MC14174BDR2 SOIC–16 2500/Tape & Reel MC14174BF SOEIAJ–16 See Note 1. MC14174BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14174B/D

MC14174B

PIN ASSIGNMENT

R

1 2

Q0 D0

3

D1

4 Q1 D2

6 Q2

7

V

8

SS

BLOCK DIAGRAM

9

CLOCK RESET

1 3

D0

4

D1

6

D2

11

D3

13

D4

14

D5

16 15 14 13 125 11 10

Q0

Q1

Q2

Q3

Q4

Q5

V

DD

Q5 D5 D4 Q4 D3 Q3 C

9

2

5

7

10

12

15

= PIN 16

V

DD

V

= PIN 8

SS

TRUTH TABLE

(Positive Logic)

Inputs Output

Clock Data Reset

010 111 X1Q

XX00

X = Don’t Care

Q

No Change

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2

MC14174B

V

DD

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Output Voltage “0” Level

= VDD or 0

V

in

ОООООООО

“1” Level

V

= 0 or V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

ОООООООО

(V

OH

DD

= 4.5 or 0.5 Vdc) = 9.0 or 1.0 Vdc) = 13.5 or 1.5 Vdc)

“1” Level = 0.5 or 4.5 Vdc) = 1.0 or 9.0 Vdc) = 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source = 4.6 Vdc) = 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

= 50 pF on all outputs, all

(C

L

ОООООООО

buffers switching)

(5.) (6.)

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

ÎÎ

V

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

ÎÎ

I

DD

ÎÎ

I

ÎÎ

Vdc

5.0 10

Î

15

5.0 10

Î

15

IL

Î

5.0 10

Î

15

IH

Î

5.0 10

Î

15

Î

5.0

Î

10

Î

15

5.0 10

Î

15 15

in

—

Î

5.0 10

Î

15

T

5.0

Î

10 15

Î

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2 — —

Î

— —

Î

—

ООООООООООООООО

SS

– 55_C

)

Max

0.05

Î

0.05 —

—

Î

—

Î

1.5

3.0

Î

4.0

Î

— —

Î

—

Î

— —

Î

—

Î

— —

—

Î

—

± 0.1

—

Î

5.0 10

Î

20

25_C

Min

ÎÎ

4.95

9.95

ÎÎ

14.95

ÎÎ

3.5

7.0

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4

ÎÎ

— — —

11

— —

— — —

Typ

0 0

Î

0

5.0 10

Î

15

Î

2.25

4.50

Î

6.75

Î

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

– 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.005

0.010

Î

0.015

IT = (1.1 µA/kHz) f + I IT = (2.3 µA/kHz) f + I IT = (3.7 µA/kHz) f + I

(4.)

Max

0.05

ÎÎ

0.05 —

—

ÎÎ

—

ÎÎ

1.5

3.0

ÎÎ

4.0

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

—

ÎÎ

—

± 0.1

7.5

ÎÎ

5.0 10

ÎÎ

20

DD DD DD

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 1.7

– 0.36

Î

– 0.9

Î

– 2.4

0.36

0.9

Î

2.4 — —

Î

— —

Î

—

125_C

Max

0.05

Î

0.05

Î

± 1.0

Î

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

T

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

150 300 600

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

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3

MC14174B

DD

Î

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

Characteristic

Output Rise and Fall Time

t

, t

TLH

t

ООООООООООООО

TLH

t

TLH

Propagation Delay Time — Clock to Q

ООООООООООООО

t

PLH

t

PLH

ООООООООООООО

t

PLH

= (1.35 ns/pF) CL + 32 ns

THL

, t

= (0.6 ns/pF) CL + 20 ns

THL

, t

= (0.4 ns/pF) CL + 20 ns

THL

, t

= (0.9 ns/pF) CL + 165 ns

PHL

, t

= (0.36 ns/pF) CL + 64 ns

PHL

, t

= (0.26 ns/pF) CL + 52 ns

PHL

Propagation Delay Time — Reset to Q

t

= (0.9 ns/pF) CL + 205 ns

ООООООООООООО

PHL

= (0.36 ns/pF) CL + 79 ns

t

PHL

ООООООООООООО

t

= (0.26 ns/pF) CL + 62 ns

PHL

Clock Pulse Width

ООООООООООООО

Reset Pulse Width

ООООООООООООО

Clock Pulse Frequency

ООООООООООООО

Clock Pulse Rise and Fall Time

ООООООООООООО

Data Setup Time

ООООООООООООО

Data Hold Time

ООООООООООООО

Reset Removal Time

ООООООООООООО

= 25_C)

A

Symbol

t

, t

TLH

ÎÎÎ

t

, t

PLH

ÎÎÎ

t

PHL

ÎÎÎ

t

WH

ÎÎÎ

t

WL

ÎÎÎ

f

cl

ÎÎÎ

t

, t

TLH

ÎÎÎ

t

su

ÎÎÎ

t

h

ÎÎÎ

t

rem

ÎÎÎ

THL

PHL

THL

V

DD

Vdc

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

5.0

ÎÎ

10

ÎÎ

15

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

Min

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

—

ÎÎ

—

150

90

ÎÎ

70

200 100

ÎÎ

80 —

ÎÎ

— —

ÎÎ

— — —

ÎÎ

40 20

ÎÎ

15 80

40

ÎÎ

30

250 100

ÎÎ

80

All Types

(8.)

Typ

100

50

ÎÎ

40

ÎÎ

210

85

ÎÎ

65

250

ÎÎ

100

ÎÎ

75 75

45

ÎÎ

35

100

50

ÎÎ

40

7.0

ÎÎ

12

15.5

ÎÎ

— — —

ÎÎ

20 10

ÎÎ

0

40 20

ÎÎ

15

125

50

ÎÎ

40

Max

200 100

ÎÎ

80

ÎÎ

400 160

ÎÎ

120

500

ÎÎ

200

ÎÎ

150

— —

ÎÎ

— —

—

ÎÎ

—

2.0

ÎÎ

5.0

6.5

ÎÎ

15

5.0

4.0

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

— —

—

ÎÎ

—

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

mHz

Î

m

Î

ns

Î

ns

Î

ns

Î

s

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4

MC14174B

TIMING DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

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5

–T–

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14174B

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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6

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14174B

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

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7

MC14174B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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MC14174B/D

Datasheet MC14174BCP, MC14174BD, MC14174BDR2, MC14174BF, MC14174BFEL Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual