Page 1
MC141540
1
MOTOROLA
CMOS
The MC141540 is a high performance HCMOS device designed to interface
with a microcontroller unit to allow colored symbols or characters to be
displayed on a color monitor. The on–chip PLL allows both multi–system
operation and self–generation of system timing. It also minimizes the MCU’s
burden through its built–in 273 bytes display/control RAM. By storing a full
screen of data and control information, this device has a capability to carry out
‘screen–refresh’ without MCU supervision.
Since there is no spacing between characters, special graphics–oriented
characters can be generated by combining two or more character blocks.
Special functions such as character bordering or shadowing, multi–level
windows, double height and double width, and programmable vertical length of
character can also be incorporated. Furthermore, neither massive information
update nor extremely high data transmission rate are expected for normal on–
screen display operation, and serial protocols are implemented in lieu of any
parallel formats to achieve minimum pin count.
• Fixed Resolution: 320 (CGA) Dots per Line
• Fully Programmable Character Array of 10 Rows by 24 Columns
• 273 Bytes Direct Mapping Display RAM Architecture
• Internal PLL Generates a Wide–Ranged System Clock
• For High–End Monitor Application, Maximum Horizontal Frequency is
100 kHz (32 MHz Dot Clock)
• Programmable Vertical Height of Character to Meet Multi–Sync
Requirement
• Programmable Vertical and Horizontal Positioning for Display Center
• 128 Characters and Graphic Symbols ROM
• 10 x 16 Dot Matrix Character
• Character–by–Character Color Selection
• A Maximum of Four Selectable Colors per Row
• Double Character Height and Double Character Width
• Character Bordering or Shadowing
• Three Fully Programmable Background Windows with Overlapping
Capability
• Single Positive 5 V Supply
• MC141540P4 is a Replacement for XC141540P with Two Symbols Added
in ROM Addresses ‘5C’ and ‘5E’
Order this document
by MC141540/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
P SUFFIX
PLASTIC DIP
CASE 648
ORDERING INFORMATION
MC141540P4 Plastic DIP
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
FBKG
B
G
R
V
SS
V
DD
VFLB
HTONE
V
DD(A
)
RP
VCO
SCL(SCK)
SDA(MOSI)
SS
HFLB
V
SS(A)
Motorola, Inc. 1997
REV 1
2/97 TN97031200
Page 2
MC141540
MOTOROLA
2
BLOCK DIAGRAM
DATA RECEIVER
BUS ARBITRATION
VERTICAL
CONTROL
CIRCUIT
HORIZONTAL
CONTROL
BACKGROUND
GENERAT OR
COLOR ENCODER
10–BIT SHIFT
REGISTER
CHARACTER ROMS
ROW
BUFFER
LOGIC
WADDR
WCOLOR
CCOLORS
CHS
CWS
CRS
WCOLOR
AND CONTROL
CCOLORS
AND SELECT
WADDR
SC
HORD
5
CCLK
DHOR
LP
4
BLACKEDGE
MCLK
SDA(MOSI)
RP
VCO
SCL(SCK)
DATA
RA,CA,DA
RFG
ADDRC
Y
9
3
8
7
8
6
10
3
2
5
54
1115 14 13 12
3
W
R
CHS
54
15
13
8
5
26
NROW
15
13
CWS
SHADOW
FBKG
HTONE
B
G
R
CHAR
CRADDR
OSD_EN
VERD
HORD
RDATA
LUMINANCE
BSEN
SHADOW
BSEN
OSD_EN
5
CH
4
AND PLL
AND
CONTROL
8
VERD
4
Z
26
8
AND SELECT
6
10
9
1
16
V
DD
VSS(A)
V
DD(A)
MCLK
V
SS
MEMORY AND DATA
MANAGEMENT
SS
VFLB
HFLB
Page 3
MC141540
3
MOTOROLA
ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V
SS
Symbol
Characteristic Value Unit
V
DD
Supply Voltage – 0.3 to + 7.0 V
V
in
Input Voltage VSS – 0.3 to
VDD + 0.3
V
Id Current Drain per Pin Excluding V
DD
and V
SS
25 mA
Ta
Operating Temperature Range 0 to 85 °C
T
stg
Storage Temperature Range – 65 to + 150 °C
NOTE: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
AC ELECTRICAL CHARACTERISTICS (V
DD
= V
DD(A)
= 5.0 V , VSS = V
SS(A)
= 0 V, TA = 25°C, Voltage Referenced to VSS)
Symbol Characteristic Min Typ Max Unit
t
r
t
f
Output Signal (R, G, B, FBKG and HTONE) C
load
= 30 pF, see Figure 1
Rise Time
Fall Time
—
—
—
—
10
10
ns
ns
F
HFLB
HFLB Input Frequency — — 100 kHz
DC CHARACTERISTICS V
DD
= V
DD(A)
= 5.0 V ± 10%, VSS = V
SS(A)
= 0 V, TA = 25°C, Voltage Referenced to V
SS
Symbol Characteristic Min Typ Max Unit
V
OH
High Level Output Voltage
I
out
= – 5 mA
VDD – 0.8 — — V
V
OL
Low Level Output Voltage
I
out
= 5 mA
— — VSS + 0.4 V
V
IL
V
IH
Digital Input Voltage (Not Including SDA and SCL)
Logic Low
Logic High
—
0.7 V
DD
—
—
0.3 V
DD
—
V
V
V
IL
V
IH
Input Voltage of Pin SDA and SCL in SPI Mode
Logic Low
Logic High
—
0.7 V
DD
—
—
0.3 V
DD
—
V
V
I
II
High–Z Leakage Current (R, G, B and FBKG) – 10 — + 10 µA
I
II
Input Current (Not Including RP, VCO, R, G, B, FBKG and HTONE)
– 10 — + 10 µA
I
DD
Supply Current (No Load on Any Output) — 9* — mA
*Not a guaranteed limit.
90%
10%
90%
10%
tf tr
Figure 1. Switching Characteristics
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Vin and V
out
be constrained to the range VSS ≤
(Vin or V
out
) ≤ VDD. Unused inputs must always
be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left
open.
Page 4
MC141540
MOTOROLA
4
PIN DESCRIPTIONS
V
SS(A)
(Pin 1)
This pin provides the signal ground to the PLL circuitry.
Analog ground for PLL operation is separated from digital
ground for optimal performance.
VCO (Pin 2)
Pin 2 is a control voltage input to regulate an internal oscillator frequency. See the Application Diagram for the application values used.
RP (Pin 3)
An external RC network is used to bias an internal VCO to
resonate at the specific dot frequency. The value of the resistor for this pin should be adjusted in order to set the pin voltage to around half VDD. See the Application Diagram for the
application values used.
V
DD(A)
(Pin 4)
Pin 4 is a positive 5 V supply for PLL circuitry. Analog power for PLL is separated from digital power for optimal performance.
HFLB
(Pin 5)
This pin inputs a negative polarity horizontal synchronize
signal pulse to phase lock an internal system clock generated by the on–chip VCO circuit.
SS
(Pin 6)
This input pin is part of the SPI serial interface. An active
low signal generated by the master device enables this slave
device to accept data. This pin should be pulled high to terminate the SPI communication.
SDA (MOSI) (Pin 7)
Data and control messages are being transmitted to this
chip from a host MCU via this wire, which is configured as a
uni–directional data line. (Detailed description of these two
protocols will be discussed in the SPI section).
SCL (SCK) (Pin 8)
A separate synchronizing clock input from the transmitter
is required for either protocol. Data is read at the rising edge
of each clock signal.
VDD (Pin 9)
This is the power pin for the digital logic of the chip.
VFLB
(Pin 10)
Similar to Pin 5, this pin inputs a negative polarity vertical
synchronize signal pulse.
HTONE (Pin 11)
This pin outputs a logic high during windowing except
when graphics or characters are being displayed. It is used
to lower the external R, G, and B amplifiers’ gain to achieve a
transparent windowing effect.
FBKG (Pin 12)
This pin outputs a logic high while displaying characters or
windows when the FBKGC bit in the frame control register is
0, and output a logic high only while displaying characters
when the FBKGC bit is 1. It is defaulted to high–impedance
state after power–on, or when there is no output. An external
10 kΩ resistor pulled low is recommended to avoid level toggling caused by hand effect when there is no output.
B,G,R (Pins 13,14,15)
MOSD color output is TTL level RGB to the host monitor.
These three signals are active high output pins that are in a
high–impedance state when MOSD is disabled.
VSS (Pin 16)
This is the ground pin for the digital logic of the chip.
SYSTEM DESCRIPTION
MC141540 is a full–screen memory architecture. Refresh
is performed by the built–in circuitry after a screenful of display data has been loaded through the serial bus. Only
changes to the display data need to be input afterward.
Serial data, which includes screen mapping address, display information, and control messages, are transmitted via
the SPI bus. Figure 2 contains the SPI protocol operating
procedure.
Data is received from the serial port and stored by the
memory management circuit. Line data is stored in a row
buffer for display and refreshing. During this storing and retrieving cycle, bus arbitration logic patrols the internal traffic
to make sure that no crashes occur between the slower serial bus receiver and the fast ‘screen–refresh’ circuitry. After
the full–screen display data is received through one of the
serial communication interfaces, the link can be terminated if
a change of the display is not required.
The bottom half of the block diagram contains the hardware functions for the entire system. It performs all the
MOSD functions such as programmable vertical length (from
16 lines to 63 lines), display clock generation (which is phase
locked to the incoming horizontal sync signal at Pin 5 HFLB
),
bordering or shadowing, and multiple windowing.
COMMUNICATION PROTOCOLS
Serial Peripheral Interface (SPI)
SPI is a three–wire serial communication link that requires
separate clock (SCK) and data (MOSI) lines. In addition, an
SS
slave select pin is controlled by the master transmitter to
initiate the receiver.
Operating Procedure
To initiate SPI transmission, the SS
pin is pulled low by the
master device to enable MC141540 to accept data. The SS
input line must be a logic low prior to the occurrence of SCK,
and remain low until and after the last (eighth) SCK cycle. After all data has been sent, the SS
pin is then pulled high by
the master to terminate the transmission. No slave address
is needed for SPI. Hence, row and column address information and display data can be sent immediately after the SPI is
initiated.
Page 5
MC141540
5
MOTOROLA
MOSI
MSB LSB
SCK
last byte
first byte
Figure 2. SPI Protocol
SS
DA TA TRANSMISSION FORMATS
After the proper identification by the receiving device, a
data train of arbitrary length is transmitted from the master.
There are three transmission formats from (a) to (c) as stated
below. The data train in each sequence consists of row address (R), column address (C), and display information (I), as
shown in Figure 3. In format (a), display information data
must be preceded with the corresponding row address and
column address. This format is particularly suitable for updating small amounts of data between different rows. However,
if the current information byte has the same row address as
the one before, format (b) is recommended.
row addr col addr info
Figure 3. Data Packet
For a full–screen pattern change that requires a massive
information update, or during power–up, most of the row and
column addresses of either (a) or (b) formats will be consecutive. Therefore, a more efficient data transmission format (c)
should be applied. This sends the RAM starting row and column addresses once only, and then treats all subsequent
data as display information. The row and column addresses
will be automatically incremented internally for each display
information data from the starting location. Because Columns 24 through 29 are unused, it is recommended that
these locations are filled with dummy data while using format
(c) to transmit.
The data transmission formats are:
(a) R – > C – > I – > R – > C – > I – > . . . . . . . . .
(b) R – > C – > I – > C – > I – > C – > I. . . . . . .
(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .
T o dif ferentiate the row and column addresses when transferring data from master, the MSB (most significant bit) is set,
as in Figure 4: ‘1’ to represent row, and ‘0’ for column address. Furthermore, to distinguish the column address between formats (a), (b), and (c), the sixth bit of the column
address is set to ‘1’ which represents format (c), and ‘0’ for
format (a) or (b). However, there is some limitation on using
mixed formats during a single transmission. It is permissible
to change the format from (a) to (b), or from (a) to (c), or from
(b) to (a), but not from (c) back to (a) or (b).
ADDRESS
ROW
COLUMN
COLUMN
X: don’t care D: valid data
FORMATBIT
01234567
DDDDXXX1
DDDDDX00
DDDDDX10
a, b
a, b, c
c
Figure 4. Row & Column Address Bit Patterns
MEMORY MANAGEMENT
Internal RAM is addressed with row and column (coln)
numbers in sequence. The spaces between Row 0 and Coln
0 to Row 9 and Coln 23 are called display registers, and each
contains a character ROM address corresponding to a display location on the monitor screen. Every data row is
associated with two control registers, which are located at
Coln 30 and 31 of their respective rows, to control the character display format of that row. In addition, three window
control registers for each of the three windows, together with
three frame control registers, occupy the first 13 columns of
Row 10.
The user should handle the internal RAM address location
with care, especially those rows with double length alphanumeric symbols. For example, if Row n is destined to be
double height on the memory map, the data displayed on
screen Rows n and n+1 will be represented by the data contained in the memory address of Row n only. The data of the
next Row n+1 on the memory map will appear on the screen
as n+2 and n+3 row space, and so on. Hence, it is not necessary to load a row of blank data to compensate for the double
row. The user should minimize excessive rows of data in
memory in order to avoid overrunning the limited amount of
row space on the screen.
For rows with double width alphanumeric symbols, only
the data contained in the even numbered columns of the
memory map are shown. Odd numbered columns are
treated in the same manner as double height rows.
DISPLAY REGISTERS
COLUMN
29 30 310
0
9
ROW
ROW CONTROL REGISTERS
WINDOW 1 WINDOW 2 FRAME CRTL REGWINDOW 3
10
0 235689 12
23 24...
WINDOW AND FRAME CONTROL REGISTERS
Figure 5. Memory Map
RESERVED SPACE
Page 6
MC141540
MOTOROLA
6
REGISTERS
Display Register
01234567
CCS0
CRADDR
Bit 7 CCS0 — This bit defines a specific character color
out of the two preset colors. Color 1 is selected if this bit is
cleared, and Color 2 otherwise.
Bit 6–0 CRADDR — These seven bits address the 128
characters or symbols residing in the character ROM.
Row Control Registers
Coln 30
01234567
CWSCHSB2G2R2B1G1R1
COLN 30
Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color
2 by R2, G2, and B2.
Bit 1 CHS — This bit determines the height of a display
symbol. When it is set, the symbol is displayed in double
height.
Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the
character is displayed in double width.
Coln 31
01234567
B4G4R4B3G3R3
COLN 31
Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color
4 by R4, G4, and B4.
Window 1 Registers
Row 10 Coln 0, 3, or 6
0
1234567
ROW END ADDR
MSB
LSB
ROW START ADDR
MSB
LSB
COLN 0,
ROW 10
3, or 6
Row 10 Coln 1, 4, or 7
WEN CCS1
COL START ADDR
MSB
LSB
COLN 1,
0
1234567
ROW 10
4, or 7
Bit 2 WEN — This bit enables the background Window 1
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 1 with two extra color
selections, making a total of four selections for that row.
Row 10 Coln 2, 5, or 8
ОООООООООООО
RG
COL END ADDR
MSB LSB
COLN 2,
0
1234567
B
ROW 10
5, or 8
Window 1 occupies Columns 0–2 of Row 10; Window 2
occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority window will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be displayed.
Frame Control Registers
Coln 9
0
1234567
LSB
COLN 9
MSB
VERTD
Bit 7–0 VERTD — These six bits define the vertical starting
position. There are a total of 64 steps, with an increment of
four horizontal lines per step for each field. The value cannot
be zero anytime, and the default value is 4.
Coln 10
01234567
LSB
COLN 10
MSB
HORD
Bit 6–0 HORD — These bits define the horizontal starting
position for character display. Five bits give a total of 32
steps and each increment represents a five–dot shift to the
right on the monitor screen. The value cannot be zero anytime, and the default value is 5.
Coln 11
7
COLN 11
6543 210
CH5 CH4 CH3 CH2 CH1 CH0
Bit 5–0 CH5–CH0 — These six bits determine the displayed character height. It is possible to have a proper character height by setting a value greater than or equal to 16 on
a different horizontal frequency monitor. Setting a value below 16 will not have a predictable result. Figure 6 illustrates
how this chip expands the built–in character font to the desired height.
Coln 12
7
OSD_EN
COLN 12
65
43
21
0
BSEN
SHADOW
FBKGC
Bit 7 OSD_EN — The OSD circuit is activated when this bit
is set.
Bit 6 BSEN — This bit enables the character bordering or
shadowing function when it is set.
Bit 5 SHADOW — Characters with black–edge shadowing
are selected if this bit is set; otherwise bordering prevails.
Bit 0 FBKGC — Bit 0 determines the configuration of the
FBKG output pin. When it is clear, the FBKG pin outputs high
while displaying characters or windows; otherwise, the
FBKG pin outputs high only while displaying characters.
Page 7
MC141540
7
MOTOROLA
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16 lines 22 lines
34 lines25 lines
Built–in font Display character
when CH=22
Display character
when CH=34when CH=25
Display character
(10x16 matrix)
when CH=16
Figure 6. Variable Character Height
An IBM PC program called “MOSD Font Editor” (Rev. 2.0)
was written for MC141540 editing purposes. This program
generates a set of S–Record or Binary record for the desired
display patterns to be masked onto the character ROM of the
MC141540.
In order to have better character display within windows, it
is suggested that the designed character font be placed in
the center of the 10 x 16 matrix with equal space on all four
sides. The character $00 is predefined for blank characters,
and the character $7F is predefined for full–filled characters.
In order to avoid submersion of displayed symbols or characters into a background of comparable colors, a feature of
bordering which encircles all four sides, or shadowing which
encircles only the right and bottom sides of an individual display character, are provided. Figure 7 shows how a character
is jacketed differently. To make sure that a character is bordered or shadowed correctly, at least one blank dot should
be reserved on each side of the character font.
Ï
Ï
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
Bordering
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
Shadowing
Figure 7. Character Bordering and Shadowing
Frame Format and Timing
Figure 8 illustrates the positions of all display characters
on the screen relative to the leading edge of horizontal and
vertical flyback signals. The shaded area indicates the area
outside the “safe viewing area” for the display characters.
Notice that there are two components in the equations stated
in Figure 8 for horizontal and vertical delays: fixed delays
from the leading edge of HFLB
and VFLB signals, regardless
of the values of HORD and VERTD (47 dots + phase detection pulse width) and one H scan line for horizontal and vertical delays, respectively; and variable delays determined by
the values of HORD and VERTD. Refer to Frame Control
Registers Coln 9 and 10 for the definitions of VERTD and
HORD.
Phase detection pulse width is a function of the external
charge–up resistor, which is the 330 kΩ resistor in a series
with 2 kΩ to VCO pin in the Application Diagram. Dot frequency is determined by the equation
H freq x 320
. For example, dot frequency is 10.24 MHz if H freq is 32 kHz.
Hence, a dot equals 1/10.24 µs.
When double character width is selected for a row, only the
even–numbered characters will be displayed, as shown in
Row 2. Notice that the total number of horizontal scan lines in
the display frame is variable, depending on the chosen character height of each row. Care should be taken while configuring each row character height so that the last horizontal
scan line in the display frame always comes out before the
leading edge of VFLB
of the next frame, to avoid wrapping
display characters of the last few rows in the current frame
into the next frame. The number of display dots in a horizontal scan line is always fixed at 240, regardless of row character width.
Page 8
MC141540
MOTOROLA
8
VFLB
HFLB
1
ROW
COLUMN
234
5
6
. . . . . .
14
123
0
0
29282726
double height
double width
CH5–0 = 0x21
CH5–0 = 0x21
& double height
standard size 10x16
& double width
col 0 col 2 col 4 col 6 col 8 col 10 col 12 col 14
col 28
10x30 dots fixed
variable number of H scan lines
vertical delay =
VERTD x 4 + 1 H scan lines
horizontal delay =
(HORD x 5 + 47) dots + phase detection pulse width
Display Frame Format
area not interfered by display characters
display character
. . . . . . . . . . . . . . . .
HFLB
Figure 8. Display Frame Format
Figure 9 illustrates the timing of all output signals as a
function of window and fast–blanking features. Line 3 of all
three characters is used to illustrate the timing signals. The
shaded area depicts the window area. The characters on the
left and right appear identical except for the FBKGC bit. The
middle character does not have a window as its background.
Notice that signal HTONE is active only in the window area.
Timing of the signal FBKG depends on the configuration of
the FBKGC bit. The configuration of the FBKGC bit affects
only the FBKG signal timing; it has no effect on the timing of
HTONE. Waveform ‘R, G, or B’, which is the actual waveform
at R, G, or B pin, is the logical OR of waveform ‘character R,
G, or B’ and waveform ‘window R, G, or B’. ‘Character R, G,
or B’ and ‘window R, G, or B’ are internal signals for illustration purpose only. Also notice that HTONE has exactly the
same waveform as ‘window R, G, or B’.
FBKG
FBKGC Bit = 0
Character Inside a Window Character Outside a Window
HTONE
FBKGC Bit = 1
Character Inside a Window
3
Line 3
Window R, G, or B
Character R, G, or B
R, G, or B
Figure 9. Timing of Output Signals as a Function
of Window and FBKGC Bit Features
FONT
Icon Combination
MC141540 contains 128–character ROM. The user can
create an on–screen menu based on those characters and
icons. Addresses $00 and $7F are predefined characters.
They cannot be modified in any MOSDs.
ROM CONTENT
Figures 10 – 13 show the ROM content of MC141540.
Mask ROM is optional for custom parts.
Page 9
MC141540
9
MOTOROLA
00
1B
01 0302
07060504
08 09 0A 0B
0F0E0D0C
10 11 12 13
17
1F
161514
1A1918
1E1D1C
Figure 10. ROM Address ($00 – $1F)
20 21 2322
24 25 2726
28 29 2B2A
2C 2D 2F2E
30 31 3332
34 35 3736
38
39 3B3A
3C 3D 3F3E
Figure 11. ROM Address ($20 – $3F)
Page 10
MC141540
MOTOROLA
10
40 41 4342
44 45 4746
48 49 4B4A
4C 4D 4F4E
50 51 5352
54 55 5756
58 59 5B5A
5C 5D 5F5E
Figure 12. ROM Address ($40 – $5F)
60 61 6362
64 65 6766
68 69 6B6A
6C 6D 6F6E
70 71 7372
74 75
77
76
78 79 7B7A
7C 7D 7F7E
Figure 13. ROM Address ($60 – $7F)
Page 11
MC141540
11
MOTOROLA
DESIGN CONSIDERA TIONS
Distortion
Motorola’s MC141540 has a built–in PLL for multi–system
application. Pin 2 voltage is dc–based for the internal VCO in
the PLL. When the input frequency (HFLB) to Pin 5 increases, the VCO frequency will increase accordingly. This
forces the PLL to a higher locked frequency output. The frequency should be equal to 320 x HFLB. This is the pixel dot
clock.
Display distortion is caused by noise on Pin 2. Positive
noise increases the VCO frequency above normal. The corresponding scan line will be shorter accordingly. In contrast,
negative noise causes the scan line to be longer. The net result will be distortion on the display, especially on the right
hand side of the display window.
In order to have distortion–free display, the following recommendations should be considered:
• Only analog part grounds (Pin 2 to Pin 4) can be con-
nected to Pin 1(V
SS(A)
). VSS and other grounds should be
connected to PCB common ground. The V
SS(A)
and V
SS
grounds should be totally separated (i.e. V
SS(A)
is floating). Refer to the Application Diagram for the ground connections.
• The dc supply path for Pin 9 (V
DD
) should be separated
from other switching devices.
• The LC filter should be connected between Pin 9 and Pin
4. Refer to the values used in the Application Diagram.
• Biasing and filter networks should be connected to Pin 2
and Pin 3. Refer to the recommended networks in the Application Diagram.
• Two small capacitors can be connected between Pins 2
and 3, and between Pins 3 and 4.
Jittering
Most display jittering is caused by HFLB jittering on Pin 5.
Care must be taken if the HFLB signal comes from the flyback transformer. A short path and shielded cable are recommended for a clean signal. A small capacitor can be
added between Pin 5 and Pin 16 to smooth the signal. Refer
to the value used in the Application Diagram.
Display Dancing
Most display dancing is caused by interference of the serial bus. It can be avoided by adding series resistors to the serial bus.
APPLICATION DIAGRAM
MPS2369
100 µH
0.1 µF
100
µ
F
ANALOG GROUND – FLOATING
3.3 k
100
100
100
240
240
240
V
CC
V
CC
1 k
1 k
1 k
0.1
µ
F
10
µ
F
9
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
0.01
µ
F
1 k
0.047
µ
F
33 pF
33 pF
100
100
100
V
DD
V
SS
R
G
B
FBKG
HTONE
VFLB
V
SS(A)
VCO
RP
HFLB
SS
SDA(MOSI)
SCL(SCK)
V
DD(A)
HFLB
2 k
VFLB
HTONE
FBKG
B
G
R
330 k
DIGITAL GROUND – COMMON GROUND
ANALOG GROUND
DIGITAL GROUND
MOSD
IIC(SPI) BUS
330 pF
Page 12
MC141540
MOTOROLA
12
P ACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
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