The MC14099B is an 8−bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read
Enable.
A Master Reset capability is available on both parts.
or Chip
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MARKING
DIAGRAMS
Features
• Serial Data Input
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
DC Supply Voltage Range−0.5 to +18.0V
DD
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation, per Package
D
Ambient Temperature Range−55 to +125°C
A
Storage Temperature Range−65 to +150°C
stg
Lead Temperature
L
ParameterValueUnit
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
)
SS
−0.5 to VDD + 0.5V
±10mA
500mW
260°C
PDIP−16
P SUFFIX
CASE 648
SOIC−16
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
A= Assembly Location
WL, L= Wafer Lot
YY, Y= Year
WW, W = Work Week
16
MC14099BCP
AWLYYWW
1
16
14099B
AWLYYWW
1
16
MC14099B
AWLYWW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
(Vin or V
SS
or VDD). Unused outputs must be left open.
SS
) VDD.
out
and V
in
should be constrained
out
1Publication Order Number:
MC14099B/D
Page 2
MC14099B
PIN ASSIGNMENT
1
Q7
DATA
2
3
4
RESET
WRITE
DISABLE
A0
A1
6
A2
7
8
V
SS
ORDERING INFORMATION
DevicePackageShipping
MC14099BCPPDIP−16500 Units / Rail
MC14099BCPGPDIP−16
MC14099BDWSOIC−16 WB47 Units / Rail
MC14099BDWGSOIC−16 WB
MC14099BDWR2SOIC−16 WB1000 Units / Tape & Reel
MC14099BDWR2GSOIC−16 WB
MC14099BFELSOEIAJ−162000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
16
V
DD
15
Q6
14
Q5
13
Q4
125
Q3
11
Q2
10
Q1
9
Q0
WRITE DISABLE
RESET
DATA
A0
A1
A2
MC14099B
5
6
DECODER
7
V
= 16
DD
V
= 8
SS
4
3
8
2
8
LATCHES
9
Q0
10
Q1
11
Q2
12
Q3
13
Q4
14
Q5
15
Q6
1
Q7
†
500 Units / Rail
(Pb−Free)
47 Units / Rail
(Pb−Free)
1000 Units / Tape & Reel
(Pb−Free)
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2
Page 3
MC14099B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
IT = (1.5 A/kHz) f + I
IT = (3.0 A/kHz) f + I
IT = (4.5 A/kHz) f + I
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
−
−
ÎÎ
−
1.5
ÎÎ
3.0
ÎÎ
4.0
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
± 0.1
7.5
22.5
ÎÎ
5.0
ÎÎ
10
20
ÎÎ
DD
DD
DD
Min
Î
−
−
−
Î
4.95
9.95
Î
14.95
−
Î
−
Î
−
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
Î
– 0.9
– 2.4
Î
0.36
0.9
Î
2.4
−
−
−
Î
−
Î
−
−
Î
125C
Max
Î
0.05
0.05
0.05
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
150
Î
300
600
Î
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk
I
T(CL
where: I
is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
T
1.5
3.0
4.0
Unit
Î
Vdc
Î
−
Vdc
−
Î
−
Vdc
Î
Î
Vdc
−
Î
−
Î
−
mAdc
−
Î
−
Î
−
−
Î
−
mAdc
−
Î
−
Adc
−
−
pF
pF
Î
Adc
Î
Î
Adc
Î
Î
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3
Page 4
MC14099B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
SWITCHING CHARACTERISTICS (Note 5) (C
= 50 pF, T
L
Characteristic
ООООООООООООО
Output Rise and Fall Time
t
, t
TLH
t
ООООООООООООО
TLH
t
TLH
Propagation Delay Time
ООООООООООООО
Data to Output Q
ООООООООООООО
Write Disable to Output Q
ООООООООООООО
ООООООООООООО
= (1.35 ns/pF) CL + 32 ns
THL
, t
= (0.6 ns/pF) CL + 20 ns
THL
, t
= (0.4 ns/pF) CL + 20 ns
THL
Reset to Output Q
ООООООООООООО
CE to Output Q (MC14599B only)
ООООООООООООО
Propagation Delay Time, MC14599B only
ООООООООООООО
Chip Enable, Write/Read
ООООООООООООО
to Data
Address to Data
ООООООООООООО
ООООООООООООО
Pulse Widths
Reset
ООООООООООООО
ООООООООООООО
Write Disable
ООООООООООООО
Set Up Time
Data to Write Disable
ООООООООООООО
ООООООООООООО
Hold Time
Write Disable to Data
ООООООООООООО
ООООООООООООО
Set Up Time
Address to Write Disable
ООООООООООООО
Removal Time
Write Disable to Address
ООООООООООООО
= 25C)
A
V
Symbol
ÎÎÎ
t
,
TLH
t
THL
ÎÎÎ
DD
Vdc
ÎÎ
5.0
10
ÎÎ
15
t
,
PHL
ÎÎÎ
t
PLH
ÎÎÎ
ÎÎ
5.0
10
ÎÎ
15
ÎÎÎ
ÎÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
ÎÎÎÎÎÎ
10
15
5.0
ÎÎÎÎÎÎ
t
,
PHL
ÎÎÎ
t
PLH
ÎÎÎ
10
15
ÎÎ
5.0
10
ÎÎ
15
5.0
ÎÎÎ
ÎÎÎ
t
w(H)
t
w(L)
ÎÎÎ
ÎÎÎ
ÎÎ
10
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
10
ÎÎÎÎÎÎ
t
su
ÎÎÎ
ÎÎÎ
t
h
ÎÎÎ
ÎÎÎ
t
su
ÎÎÎ
t
rem
ÎÎÎ
15
5.0
ÎÎ
10
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
10
ÎÎ
15
5.0
10
ÎÎ
15
Min
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
150
ÎÎ
75
50
ÎÎ
320
160
120
ÎÎ
100
ÎÎ
50
35
ÎÎ
150
ÎÎ
75
50
ÎÎ
100
80
ÎÎ
40
0
0
ÎÎ
0
Typ
(Note 6)
ÎÎ
100
50
ÎÎ
40
ÎÎ
200
75
ÎÎ
50
200
ÎÎ
80
60
ÎÎ
175
80
ÎÎ
65
225
100
ÎÎ
75
ÎÎ
200
80
ÎÎ
65
200
ÎÎ
90
75
ÎÎ
75
ÎÎ
40
25
ÎÎ
160
80
60
ÎÎ
50
ÎÎ
25
20
ÎÎ
75
ÎÎ
40
25
ÎÎ
45
30
ÎÎ
10
– 80
– 40
ÎÎ
– 40
Max
ÎÎ
200
100
ÎÎ
80
ÎÎ
400
150
ÎÎ
100
400
ÎÎ
160
120
ÎÎ
350
160
ÎÎ
130
450
200
ÎÎ
150
ÎÎ
400
160
ÎÎ
130
400
ÎÎ
180
150
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
−
−
ÎÎ
−
5. The formulas given are for the typical characteristics only at 25C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
Î
ns
Î
ns
Î
Î
ns
Î
Î
ns
Î
ns
Î
ns
Î
Î
ns
Î
Î
ns
Î
Î
ns
Î
ns
Î
Î
ns
Î
Î
ns
Î
ns
Î
http://onsemi.com
4
Page 5
RESET
DATA
WRITE
DISABLE
A0
A1
A2
(M.S.B.)
MC14099B
FUNCTION DIAGRAM
2
9Q0
3
4
EACH LATCH
TO
OTHER
LATCHES
5
6
7
ADDRESS
DECODER
ZERO
SELECT
OTHER LATCHES
10Q1
11Q2
12Q3
13Q4
14Q5
15Q6
1Q7
TRUTH TABLE
Write
Disable
00DataQn*
01DataReset
10Qn*Qn*
11ResetReset
*Qn is previous state of latch.
†Reset to zero state.
Reset
Addressed
Latch
Unaddressed
Latches
CAUTION: To avoid unintentional data changes in the latches, Write
Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
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5
Page 6
DATA OR
WRITE DISABLE
50%
MC14099B
SWITCHING WAVEFORMS
V
DD
V
SS
OUTPUT Q
RESET
OUTPUT Q
t
PLH
50%
10%
90%
50%
t
TLH
t
w(H)
t
PHL
V
DD
ADDRESS
t
THL
WRITE
DISABLE
V
DD
V
SS
t
PHL
DATA
50%
t
50%
V
SS
su
t
w(L)
t
rem
V
DD
50%
V
SS
t
su
t
h
V
DD
V
SS
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6
Page 7
MC14099B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
−A−
916
B
18
F
C
S
SEATING
−T−
PLANE
H
G
D
16 PL
0.25 (0.010)T
K
M
A
L
J
M
SOIC−16 WB
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G−03
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MINMAXMINMAX
A 0.740 0.770 18.80 19.55
B 0.250 0.2706.356.85
C 0.145 0.1753.694.44
D 0.015 0.0210.390.53
F 0.0400.701.021.77
M
G0.100 BSC2.54 BSC
H0.050 BSC1.27 BSC
J 0.008 0.0150.210.38
K 0.110 0.1302.803.30
L 0.295 0.3057.507.74
M0 10 0 10
S 0.020 0.0400.511.01
MILLIMETERSINCHES
169
M
B
H8X
M
0.25
0.25B
14X
D
A
E
h X 45
81
B16X
M
S
A
T
B
S
A
SEATING
T
PLANE
C
e
A1
L
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MINMAXMINMAX
−−−2.05−−− 0.081
A
A
0.050.20 0.002 0.008
1
0.350.50 0.014 0.020
b
0.180.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.105.45 0.201 0.215
E
1.27 BSC0.050 BSC
e
H
7.408.20 0.291 0.323
E
0.500.85 0.020 0.033
L
L
1.101.50 0.043 0.059
E
0
M
Q
0.700.90 0.028 0.035
1
−−−0.78−−− 0.031
Z
INCHES
10
10
0
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC14099B/D
8
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