Datasheet MC14094BFR1, MC14094BFR2, MC14094BDTR2, MC14094BF, MC14094BFEL Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14094B/D

MC14094B

8-Stage Shift/Store Register
with Three-State Outputs

The MC14094B combines an 8–stage shift register with a data latch

for each stage and a three–state output from each latch.

Data is shifted on the positive clock transition and is shifted from the

seventh stage to two serial outputs. The Q

S

output data is for use in

high–speed cascaded systems. The Q′S output data is shifted on the
following negative clock transition for use in low–speed cascaded
systems.

Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.

Outputs of the eight data latches are controlled by three–state
buffers which are placed in the high–impedance state by a logic Low
on Output Enable.

• Three–State Outputs

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

• Input Diode Protection

• Data Latch

• Dual Outputs for Data Out on Both Positive and

Negative Clock Transitions

• Useful for Serial–to–Parallel Data Conversion

• Pin–for–Pin Compatible with CD4094B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

Device Package Shipping

ORDERING INFORMATION

MC14094BCP PDIP–16 2000/Box
MC14094BD SOIC–16

http://onsemi.com

48/Rail
MC14094BDR2 SOIC–16 2500/Tape & Reel
MC14094BDT TSSOP–16 96/Rail
MC14094BDTR2 TSSOP–16

2500/Tape & Reel

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14094BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

TSSOP–16
DT SUFFIX

CASE 948F

1

16

14094B

AWLYWW

14

094B

ALYW

1

16

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14094B

AWLYWW

MC14094BF SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the

SOIC packages, please contact your local ON
Semiconductor representative.

MC14094B

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2

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q7

Q6

Q5

OUTPUT
ENABLE

V

DD

Q

S

Q′

S

Q8

Q1

CLOCK

DATA

STROBE

V

SS

Q4

Q3

Q2

PIN ASSIGNMENT

Output

Parallel Outputs Serial Outputs

Clock

Output

Enable

Strobe Data

Q1 Q

N

QS* Q′

S

0 X X Z Z Q7 No Chg.
0 X X Z Z No Chg. Q7
1 0 X No Chg. No Chg. Q7 No Chg.
1 1 0 0 QN–1 Q7 No Chg.
1 1 1 1 QN–1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7

Z = High Impedance X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q

S

.

MC14094B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

“1” Level

V

in

= 0 or V

DD

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

Î

Î

– 4.2
– 0.88
– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

mAdc

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

I

OL

Î

Î

5.0
10
15

Î

Î

0.64

1.6

4.2

Î

Î

—
—
—

ÎÎ

Î

0.51

1.3

3.4

Î

Î

0.88

2.25

8.8

ÎÎ

Î

—
—
—

Î

Î

0.36

0.9

2.4

Î

Î

—
—
—

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ОООООООО

Î

Input Capacitance

(V

in

= 0)

ÎÎ

Î

C

in

Î

Î

—

Î

Î

—

Î

Î

—

ÎÎ

Î

—

Î

Î

5.0

ÎÎ

Î

7.5

Î

Î

—

Î

Î

—

Î

Î

pF

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

I

DD

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

5.0
10
20

ÎÎ

Î

—
—
—

Î

Î

0.005

0.010

0.015

ÎÎ

Î

5.0
10
20

Î

Î

—
—
—

Î

Î

150
300
600

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (4.1 µA/kHz) f + I

DD

IT = (14 µA/kHz) f + I

DD

IT = (140 µA/kHz) f + I

DD

Î

Î

Î

Î

Î

Î

µAdc

3–State Output Leakage Current

I

TL

15

—

± 0.1

—

± 0.0001

± 0.1

—

± 3.0

µA

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14094B

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4

SWITCHING CHARACTERISTICS

(7.)

(CL = 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Vdc

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise and Fall Time

t

TLH

, t

THL

= (1.35 ns/pF) CL + 33 ns

t

TLH

, t

THL

= (0.6 ns/pF) CL + 20 ns

t

TLH

, t

THL

= (0.4 ns/pF) CL + 20 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time

Clock to Serial out QS

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 305 ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 107 ns

t

PLH

, t

PHL

= (0.26 ns/pF) C L + 82 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

350
125

95

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

600
250
190

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Clock to Serial out Q’S

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 350 ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 149 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 62 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

230
110

75

ÎÎ

Î

ÎÎ

Î

460
220
150

Î

Î

Î

Î

ООООООООООООО

Î

ООООООООООООО

Î

Clock to Parallel out

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 375 ns

t

PLH

, t

PHL

= (0.35 ns/pF) CL + 177 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 122 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

420
195
135

ÎÎ

Î

ÎÎ

Î

840
390
270

Î

Î

Î

Î

ООООООООООООО

Î

Strobe to Parallel out

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 245 ns

t

PLH

, t

PHL

= (0.36 ns/pF) C L + 127 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 87 ns

ÎÎÎÎÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

290
145
100

ÎÎ

Î

580
290
200

Î

Î

ООООООООООООО

Î

ООООООООООООО

Î

Output Enable to Output

t

PHZ

, t

PZL

= (0.90 ns/pF) CL + 95 ns

t

PHZ

, t

PZL

= (0.36 ns/PF) CL + 57 ns

t

PHZ

, t

PZL

= (0.26 ns/pF) CL + 42 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PHZ

,

t

PZL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

140

75
55

ÎÎ

Î

ÎÎ

Î

280
150

110

Î

Î

Î

Î

ООООООООООООО

Î

ООООООООООООО

Î

t

PLZ

, t

PZH

= (0.90 ns/pF) CL + 180 ns

t

PLZ

, t

PZH

= (0.36 ns/pF) CL + 77 ns

t

PLZ

, t

PZH

= (0.26 ns/pF) CL + 57 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLZ

,

t

PZH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

225

95
70

ÎÎ

Î

ÎÎ

Î

450
190
140

Î

Î

Î

Î

ООООООООООООО

Î

Setup Time

Data in to Clock

ÎÎÎ

Î

t

su

ÎÎ

Î

5.0
10
15

ÎÎ

Î

125

55
35

ÎÎ

Î

60
30
20

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Hold Time

Clock to Data

ÎÎÎ

Î

t

h

ÎÎ

Î

5.0
10
15

ÎÎ

Î

0
20
20

ÎÎ

Î

– 40
– 10

0

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Width, High

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

200
100

83

ÎÎ

Î

100

50
40

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Clock Rise and Fall Time

ÎÎÎ

Î

t

r(cl)

t

f(cl)

ÎÎ

Î

5
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

—
—
—

ÎÎ

Î

15

5.0

4.0

Î

Î

µs

ООООООООООООО

Î

Clock Pulse Frequency

ÎÎÎ

Î

f

cl

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

2.5

5.0

6.0

ÎÎ

Î

1.25

2.5

3.0

Î

Î

MHz

ООООООООООООО

Î

ООООООООООООО

Î

Strobe Pulse Width

ÎÎÎ

Î

ÎÎÎ

Î

t

WL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

200

80
70

ÎÎ

Î

ÎÎ

Î

100

40
35

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14094B

http://onsemi.com

5

3–STATE TEST CIRCUIT

FOR t

PHZ

AND t

PZH

V

SS

FOR t

PLZ

AND t

PZL

V

DD

1 k

OUTPUT

50 pF

O.E.

CLOCK

ST

DATA

REGISTER STAGE 1

BLOCK DIAGRAM

LATCH 1 3–STATE BUFFER 1

15

2

SERIAL
DATA IN

OUTPUT
ENABLE

CLOCK CLOCK

STROBE

CLOCK

CLOCK

CLOCK

CLOCK

STROBE STROBE

STROBE

V

DD

4

5

6

7

14

13

12

11

10

9

Q1

Q2

Q′

S

Q3

Q4

Q5

Q6

Q7

Q8

Q

S

2

3

4

5

6

7

8

REGISTER STAGE 2

REGISTER STAGE 3

REGISTER STAGE 4

REGISTER STAGE 5

REGISTER STAGE 6

REGISTER STAGE 7

REGISTER STAGE 8

LATCH 2

LATCH 3

LATCH 4

LATCH 5

LATCH 6

LATCH 7

LATCH 8

3–STATE BUFFER 2

3–STATE BUFFER 3

3–STATE BUFFER 4

3–STATE BUFFER 5

3–STATE BUFFER 6

3–STATE BUFFER 7

3–STATE BUFFER 8

CLOCK CLOCK

STROBE STROBE

CLOCK

CLOCK

CLOCK

CLOCK

CLOCK

CLOCK
STROBE

STROBE

CLOCK

STROBE

3

1

*Input Protection Diodes

*

*

*

*

MC14094B

http://onsemi.com

6

10

DYNAMIC TIMING DIAGRAM

3

15

CLOCK

2

DATA IN

1

STROBE

OUTPUT
ENABLE

N

Q1 ³ Q7

9

Q

S

Q′

S

t

WH

50%

t

su

t

h

t

WL

50%

t

r

t

f

90%

10%

50% 50%

t

PZL

t

PZH

t

PHZ

t

PHL

t

PLH

t

PLH

t

PLZ

10%

90%

10%

90%90%

90%

10%

10%

50%

50%

50%

50%

t

PHL

t

PLH

t

THL

t

TLH

t

PLH

t

PHL

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

MC14094B

http://onsemi.com

7

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

TSSOP–16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC14094B

http://onsemi.com

8

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

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