Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14094B
The MC14094B combines an 8–stage shift register with a data latch for
each stage and a three–state output from each latch.
Data is shifted on the p ositive clock transition and is shifted from the
seventh stage to two serial o utputs. The QS output data is f or use in
high–speed c ascaded systems. The Q′S output data is shifted on the
following negative clock transition for use in low–speed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by three–state buffers
which are placed in the high–impedance state by a logic Low on Output
Enable.
• Three–State Outputs
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
• Useful for Serial–to–Parallel Data Conversion
• Pin–for–Pin Compatible with CD4094B
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Output
Parallel Outputs Serial Outputs
Clock
Output
Enable
Strobe
Data
Q1 Q
N
QS* Q′
S
0 X X Z Z Q7 No Chg.
0 X X Z Z No Chg. Q7
1 0 X No Chg. No Chg. Q7 No Chg.
1 1 0 0 QN–1 Q7 No Chg.
1 1 1 1 QN–1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Don’t Care
*At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q7
Q6
Q5
OUTPUT
ENABLE
V
DD
Q
S
Q
′
S
Q8
Q1
CLOCK
DATA
STROBE
V
SS
Q4
Q3
Q2
PIN ASSIGNMENT
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
Page 2
MOTOROLA CMOS LOGIC DATAMC14094B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (4.1 µA/kHz) f + I
DD
IT = (14 µA/kHz) f + I
DD
IT = (140 µA/kHz) f + I
DD
µAdc
3–State Output Leakage Current
I
TL
15
—
± 0.1
—
± 0.0001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 3.0
µA
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14094B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
V
DD
Vdc
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.35 ns/pF) CL + 33 ns
t
TLH
, t
THL
= (0.6 ns/pF) CL + 20 ns
t
TLH
, t
THL
= (0.4 ns/pF) CL + 20 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
TLH
,
t
THL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Serial out QS
t
PLH
, t
PHL
= (0.90 ns/pF) CL + 305 ns
t
PLH
, t
PHL
= (0.36 ns/pF) CL + 107 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C L + 82 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLH
,
t
PHL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
350
125
95
600
250
190
ns
Clock to Serial out Q’S
t
PLH
, t
PHL
= (0.90 ns/pF) CL + 350 ns
t
PLH
, t
PHL
= (0.36 ns/pF) CL + 149 ns
t
PLH
, t
PHL
= (0.26 ns/pF) CL + 62 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
230
110
75
460
220
150
Clock to Parallel out
t
PLH
, t
PHL
= (0.90 ns/pF) CL + 375 ns
t
PLH
, t
PHL
= (0.35 ns/pF) CL + 177 ns
t
PLH
, t
PHL
= (0.26 ns/pF) CL + 122 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
420
195
135
840
390
270
Strobe to Parallel out
t
PLH
, t
PHL
= (0.90 ns/pF) CL + 245 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C L + 127 ns
t
PLH
, t
PHL
= (0.26 ns/pF) CL + 87 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
290
145
100
580
290
200
Output Enable to Output
t
PHZ
, t
PZL
= (0.90 ns/pF) CL + 95 ns
t
PHZ
, t
PZL
= (0.36 ns/PF) CL + 57 ns
t
PHZ
, t
PZL
= (0.26 ns/pF) CL + 42 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHZ
,
t
PZL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
140
75
55
280
150
110
PHZ
, t
PZL
= (0.26 ns/pF) CL + 42 ns
t
PLZ
, t
PZH
= (0.90 ns/pF) CL + 180 ns
t
PLZ
, t
PZH
= (0.36 ns/pF) CL + 77 ns
t
PLZ
, t
PZH
= (0.26 ns/pF) CL + 57 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLZ
,
t
PZH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
225
95
70
450
190
140
Setup Time
Data in to Clock
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
su
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
125
55
35
60
30
20
—
—
—
ns
Hold Time
Clock to Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
h
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
0
20
20
– 40
– 10
0
—
—
—
ns
Clock Pulse Width, High
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
WH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
200
100
83
100
50
40
—
—
—
ns
Clock Rise and Fall Time
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
r(cl)
t
f(cl)
5
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
—
—
—
15
5.0
4.0
µs
Clock Pulse Frequency
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
f
cl
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
2.5
5.0
6.0
1.25
2.5
3.0
MHz
Strobe Pulse Width
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
WL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
200
80
70
100
40
35
—
—
—
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3–STATE TEST CIRCUIT
FOR t
PHZ
AND t
PZH
V
SS
FOR t
PLZ
AND t
PZL
V
DD
1 k
OUTPUT
50 pF
O.E.
CLOCK
ST
DATA
Page 4
MOTOROLA CMOS LOGIC DATAMC14094B
4
10
REGISTER STAGE 1
BLOCK DIAGRAM
LATCH 1 3–STATE BUFFER 1
15
2
SERIAL
DATA IN
OUTPUT
ENABLE
CLOCK CLOCK
STROBE
CLOCK
CLOCK
CLOCK
CLOCK
STROBE STROBE
STROBE
V
DD
4
5
6
7
14
13
12
11
10
9
Q1
Q2
Q
′
S
Q3
Q4
Q5
Q6
Q7
Q8
Q
S
2
3
4
5
6
7
8
REGISTER STAGE 2
REGISTER STAGE 3
REGISTER STAGE 4
REGISTER STAGE 5
REGISTER STAGE 6
REGISTER STAGE 7
REGISTER STAGE 8
LATCH 2
LATCH 3
LATCH 4
LATCH 5
LATCH 6
LATCH 7
LATCH 8
3–STATE BUFFER 2
3–STATE BUFFER 3
3–STATE BUFFER 4
3–STATE BUFFER 5
3–STATE BUFFER 6
3–STATE BUFFER 7
3–STATE BUFFER 8
CLOCK CLOCK
STROBE STROBE
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
STROBE
STROBE
CLOCK
STROBE
3
1
*Input Protection Diodes
DYNAMIC TIMING DIAGRAM
3
15
CLOCK
2
DATA IN
1
STROBE
OUTPUT
ENABLE
N
Q1 ³ Q7
9
Q
S
Q
′
S
t
WH
50%
t
su
t
h
t
WL
50%
t
r
t
f
90%
10%
50% 50%
t
PZL
t
PZH
t
PHZ
t
PHL
t
PLH
t
PLH
t
PLZ
10%
90%
10%
90%90%
90%
10%
10%
50%
50%
50%
50%
t
PHL
t
PLH
t
THL
t
TLH
t
PLH
t
PHL
*
*
*
*
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14094B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATAMC14094B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14094B/D
*MC14094B/D*
◊
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