Datasheet MC14082BDR2, MC14082BF, MC14082BFR2, MC14082BCP, MC14081BFL2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 1

1 Publication Order Number:

MC14001B/D

MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

• Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

• Pin–for–Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 1.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 2.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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Device Description

DEVICE INFORMATION

MC14001B Quad 2–Input NOR Gate
MC1401 1B Quad 2–Input NAND Gate
MC14023B Triple 3–Input NAND Gate
MC14025B Triple 3–Input NOR Gate
MC14071B Quad 2–Input OR Gate

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC140XXBCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14
DT SUFFIX

CASE 948G

1

14

140XXB

AWLYWW

14

0XXB

ALYW

1

14

XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC140XXB

AWLYWW

MC14073B Triple 3–Input AND Gate
MC14081B Quad 2–Input AND Gate

MC14082B Dual 4–Input AND Gate

See detailed ordering and shipping information in the package
dimensions section on page 1 1 of this data sheet.

ORDERING INFORMATION

MC14001B Series

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2

LOGIC DIAGRAMS

1
2

5
6

8
9

12
13

3

4

10

11

1
2

5
6

8
9

12
13

3

4

10

11

1
2

5
6

8
9

12
13

3

4

10

11

1
2

5
6

8
9

12
13

3

4

10

11

2 INPUT

1
2

9

3 INPUT

8
3

4

6

5

11
12

10

13

1
2

9

8
3

4

6

5

11
12

10

13

1
2

9

8
3

4

6

5

11
12

10

13

1

13

3
4
5

2

10
11
12

9

NC = 6, 8

VDD = PIN 14

V

SS

= PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2–Input NOR Gate

MC14025B

Triple 3–Input NOR Gate

MC14023B

Triple 3–Input NAND Gate

NAND

MC14011B

Quad 2–Input NAND Gate

OR

MC14071B

Quad 2–Input OR Gate

AND

MC14081B

Quad 2–Input AND Gate

MC14073B

Triple 3–Input AND Gate

MC14082B

Dual 4–Input AND Gate

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

OUT

D

IN 1

D

IN 2

D

V

DD

IN 1

C

IN 2

C

OUT

B

OUT

A

IN 2

A

IN 1

A

V

SS

IN 2

B

IN 1

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

OUT

D

IN 1

D

IN 2

D

V

DD

IN 1

C

IN 2

C

OUT

B

OUT

A

IN 2

A

IN 1

A

V

SS

IN 2

B

IN 1

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

IN 1

C

IN 2

C

IN 3

C

V

DD

IN 3

A

OUT

A

IN 2

B

IN 1

B

IN 2

A

IN 1

A

V

SS

OUT

B

IN 3

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

IN 1

C

IN 2

C

IN 3

C

V

DD

IN 3

A

OUT

A

IN 2

B

IN 1

B

IN 2

A

IN 1

A

V

SS

OUT

B

IN 3

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

OUT

D

IN 1

D

IN 2

D

V

DD

IN 1

C

IN 2

C

OUT

B

OUT

A

IN 2

A

IN 1

A

V

SS

IN 2

B

IN 1

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

IN 1

C

IN 2

C

IN 3

C

V

DD

IN 3

A

OUT

A

IN 2

B

IN 1

B

IN 2

A

IN 1

A

V

SS

OUT

B

IN 3

B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

OUT

D

IN 1

D

IN 2

D

V

DD

IN 1

C

IN 2

C

OUT

B

OUT

A

IN 2

A

IN 1

A

V

SS

IN 2

B

IN 1

B

11

12

13

14

8

9

105

4

3

2

1

7

6

IN 2

B

IN 3

B

IN 4

B

OUT

B

V

DD

NC

IN 1

B

IN 3

A

IN 2

A

IN 1

A

OUT

A

V

SS

NC

IN 4

A

NC = NO CONNECTION

MC14023B

Triple 3–Input NAND Gate

MC14001B

Quad 2–Input NOR Gate

MC14011B

Quad 2–Input NAND Gate

MC14082B

Dual 4–Input AND Gate

MC14081B

Quad 2–Input AND Gate

MC14025B

Triple 3–Input NOR Gate

MC14071B

Quad 2–Input OR Gate

MC14073B

Triple 3–Input AND Gate

MC14001B Series

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(3.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

“1” Level

V

in

= 0 or V

DD

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

Î

Î

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

mAdc

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

I

OL

Î

Î

5.0
10
15

Î

Î

0.64

1.6

4.2

Î

Î

—
—
—

ÎÎ

Î

0.51

1.3

3.4

Î

Î

0.88

2.25

8.8

ÎÎ

Î

—
—
—

Î

Î

0.36

0.9

2.4

Î

Î

—
—
—

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ОООООООО

Î

Input Capacitance

(V

in

= 0)

ÎÎ

Î

C

in

Î

Î

—

Î

Î

—

Î

Î

—

ÎÎ

Î

—

Î

Î

5.0

ÎÎ

Î

7.5

Î

Î

—

Î

Î

—

Î

Î

pF

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

I

DD

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.25

0.5

1.0

ÎÎ

Î

—
—
—

Î

Î

0.0005

0.0010

0.0015

ÎÎ

Î

0.25

0.5

1.0

Î

Î

—
—
—

Î

Î

7.5
15
30

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(4.) (5.)

(Dynamic plus Quiescent,
Per Gate, C

L

= 50 pF)

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.3 µA/kHz) f + IDD/N
I

T

= (0.6 µA/kHz) f + IDD/N

I

T

= (0.9 µA/kHz) f + IDD/N

Î

Î

Î

Î

µAdc

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

per package.

MC14001B Series

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4

B–SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS

(6.)

(CL = 50 pF, T

A

= 25_C)

ООООООООООООО

Î

Characteristic

ÎÎÎ

Î

Symbol

ÎÎ

Î

V

DD

Vdc

ÎÎ

Î

Min

ÎÎ

Î

Typ

(7.)

ÎÎ

Î

Max

Î

Î

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise Time, All B–Series Gates

t

TLH

= (1.35 ns/pF) CL + 33 ns

t

TLH

= (0.60 ns/pF) CL + 20 ns

t

TLH

= (0.40 ns/PF) CL + 20 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Output Fall Time, All B–Series Gates

t

THL

= (1.35 ns/pF) CL + 33 ns

t

THL

= (0.60 ns/pF) CL + 20 ns

t

THL

= (0.40 ns/pF) CL + 20 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time

MC14001B, MC14011B only

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 80 ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 32 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 27 ns

All Other 2, 3, and 4 Input Gates

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 115 ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 47 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 37 ns

8–Input Gates (MC14068B, MC14078B)

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 155 ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 62 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 47 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

, t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

5.0
10
15

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

—
—
—

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

125

50
40

160

65
50

200

80
60

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

250
100

80

300
130
100

350
150
110

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ns

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

V

DD

14

C

L

VSS7

PULSE

GENERATOR

INPUT

OUTPUT

90%

50%

10%

10%

50%

90%

20 ns 20 ns

t

PHL

t

PLH

t

TLH

t

THL

V

OL

V

OH

0 V

V

DD

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to V

SS

.

90%

50%

10%

V

OL

V

OH

OUTPUT

NON–INVERTING

t

THL

t

TLH

t

PLH

t

PHL

*

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B Series

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5

CIRCUIT SCHEMA TIC

NOR, OR GA TES

14

*

7

V

SS

3, 4, 10, 11

V

DD

V

SS

V

DD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

14

*

7

9, 6, 10

V

SS

V

DD

1, 3, 11

2, 4, 12

V

SS

V

DD

V

SS

V

DD

8, 5, 13

MC14001B, MC14071B

One of Four Gates Shown

MC14025B

One of Three Gates Shown

*Inverter omitted in MC14025B

CIRCUIT SCHEMA TIC

NAND, AND GA TES

14

*

7

3, 4, 10, 11

V

SS

V

DD

*Inverter omitted in MC14011B

14

*

7

9, 6, 10

V

SS

V

DD

*Inverter omitted in MC14023B

2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

V

DD

V

DD

V

SS

V

SS

8, 5, 13

MC14011B, MC14081B

One of Four Gates Shown

MC14023B, MC14073B

One of Three Gates Shown

MC14001B Series

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6

TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURRENT (SOURCE)

– 40°C

+ 85°C

+ 125°C

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

1.0

3.0

5.0

4.0

2.0

0

1.0 3.0 5.04.02.00

V

DS

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

– 1.0

0

0

TA = – 55°C

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

16
14
12
10

8.0

6.0

4.0

2.0
0

5.03.01.0 108.06.04.02.00

0

0

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

0

0

0

0

– 40°C

+ 25°C

+ 85°C

+ 125°C

– 1.0 – 3.0 – 5.0– 4.0– 2.0

V

DS

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

TA = – 55°C

+ 25°C

TA = – 55°C

– 40°C
+ 25°C

+ 85°C
+ 125°C

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

V

DS

, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

TA = – 55°C

– 40°C

+ 25°C

+ 85°C

+ 125°C

18

20

9.07.0 – 5.0– 3.0– 1.0 – 10– 8.0– 6.0– 4.0– 2.0 – 9.0– 7.0

– 40
– 35
– 30
– 25
– 20
– 15
– 10

– 5.0

– 45

– 50

106.02.0 2016128.04.0 1814

TA = – 55°C

– 40°C

+ 25°C

+ 85°C

– 10– 6.0– 2.0 – 20– 16– 12– 8.0– 4.0 – 18– 14

– 80
– 70
– 60
– 50
– 40
– 30
– 20
– 10

– 90

– 100

40
35
30
25
20
15
10

5.0

45

50

TA = – 55°C

– 40°C

+ 25°C

+ 85°C

– 2.0

– 3.0

– 4.0

– 5.0

– 6.0

– 7.0

– 8.0

– 9.0

– 10

I ,

D

DRAIN CURRENT (mA)

I ,

D

DRAIN CURRENT (mA)

I ,

D

DRAIN CURRENT (mA)

I ,

D

DRAIN CURRENT (mA)

I ,

D

DRAIN CURRENT (mA)

I ,

D

DRAIN CURRENT (mA)

+ 125°C

+ 125°C

These typical curves are not guarantees, but are design aids.

Caution: The maximum rating for output current is 10 mA per pin.

MC14001B Series

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7

TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

1.0

3.0

5.0

4.0

2.0

0

1.0 3.0 5.04.02.00

0

0

V

in

, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0
V

in

, INPUT VOLTAGE (Vdc)

V ,

out

OUTPUT VOLTAGE (Vdc)

V ,

out

OUTPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

0

0

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0
V

in

, INPUT VOLTAGE (Vdc)

12

14

16

V ,

out

OUTPUT VOLTAGE (Vdc)

DC NOISE MARGIN

The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V

IL

and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.

Guaranteed minimum noise margins for both the “1” and

“0” levels =

1.0 V with a 5.0 V supply

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

Figure 11. DC Noise Immunity

V

out

V

O

V

O

V

IL

0

V

IH

V

in

V

DD

V

DD

V

out

V

O

V

O

V

IL

0

V

IH

V

in

V

DD

V

DD

(a) Inverting Function (b) Non–Inverting Function

VSS = 0 VOLTS DC

MC14001B Series

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8

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L

M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC14001B Series

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9

P ACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

MC14001B Series

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10

P ACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035
––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L
DETAIL P

M

A

b
c
D
E
e

0.50

M

Z

MC14001B Series

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11

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14001BCP PDIP–14 2000 Units per Box
MC14001BD SOIC–14 2750 Units per Box
MC14001BDR2 SOIC–14 2500 Units / Tape & Reel
MC14001BDT TSSOP–14 96 Units per Rail
MC14001BDTR2 TSSOP–14 96 Units per Rail

MC1401 1BCP PDIP–14 2000 Units per Box
MC1401 1BD SOIC–14 2750 Units per Box
MC1401 1BDR2 SOIC–14 2500 Units / Tape & Reel
MC1401 1BDT TSSOP–14 96 Units per Rail
MC1401 1BDTEL TSSOP–14 2000 Units / Tape & Reel
MC1401 1BDTR2 TSSOP–14 50 Units per Rail

MC14023BCP PDIP–14 2000 Units per Box
MC14023BD SOIC–14 2750 Units per Box
MC14023BDR2 SOIC–14 2500 Units / Tape & Reel

MC14025BCP PDIP–14 2000 Units per Box
MC14025BD SOIC–14 2750 Units per Box
MC14025BDR2 SOIC–14 2500 Units / Tape & Reel

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14071BCP PDIP–14 2000 Units per Box
MC14071BD SOIC–14 55 Units per Rail
MC14071BDR2 SOIC–14 2500 Units / Tape & Reel
MC14071BDT TSSOP–14 96 Units per Rail
MC14071BDTR2 TSSOP–14 96 Units per Rail

MC14073BCP PDIP–14 2000 Units per Box
MC14073BD SOIC–14 55 Units per Rail
MC14073BDR2 SOIC–14 2500 Units / Tape & Reel

MC14081BCP PDIP–14 2000 Units per Box
MC14081BD SOIC–14 55 Units per Rail
MC14081BDR2 SOIC–14 2500 Units / Tape & Reel
MC14081BDT TSSOP–14 96 Units per Rail
MC14081BDTR2 TSSOP–14 2500 Units / Tape & Reel

MC14082BCP PDIP–14 2000 Units per Box
MC14082BD SOIC–14 55 Units per Rail
MC14082BDR2 SOIC–14 2500 Units / Tape & Reel

For ordering information on the EIAJ version of the SOIC pack­ages, please contact your local ON Semiconductor representa­tive.

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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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PUBLICATION ORDERING INFORMATION

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4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
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ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC14001B/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
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