Datasheet MC14076BD, MC14076BDR2, MC14076BCP Datasheet (MOTOROLA)

MC14076B

4-Bit D-Type Register with Three-State Outputs

The MC14076B 4–Bit Register consists of four D–type flip–flops operating synchronously from a common clock. OR gated output–disable inputs force the outputs into a high–impedance state for use in bus organized systems. OR gated data–disable inputs cause the Q outputs to be fed back to the D inputs of the flip–flops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flip–flops simultaneously independent of the clock or disable inputs.

• Three–State Outputs with Gated Control Lines

• Fully Independent Clock Allows Unrestricted Operation for the T wo

Modes: Parallel Load and Do Nothing

• Asynchronous Master Reset

• Four Bus Buffer Registers

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving T wo Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated T emperature Range

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

DD

Vin, V

Iin, I

P

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

D

A

L

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation,

per Package (Note 2.) Ambient Temperature Range –55 to +125 °C Storage Temperature Range –65 to +150 °C Lead Temperature

(8–Second Soldering)

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14076BCP

AWLYYWW

1

16

14076B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14076BCP PDIP–16 2000/Box MC14076BD SOIC–16 2400/Box MC14076BDR2 SOIC–16 2500/Tape & Reel

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

SS

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

v (Vin or V

SS

or VDD). Unused outputs must be left open.

) v VDD.

out

and V

in

should be constrained

out

1 Publication Order Number:

MC14076B/D

MC14076B

Data

Output

PIN ASSIGNMENT

OUTPUT

DISABLE

15 14 13 12 11 10

1

A

{

2

B

Q0

3 4

Q1 Q2 Q3

6 7

C

8

V

SS

BLOCK DIAGRAM

RESET D0 D1 D2 D3

DATA

B

DISABLE

A

9 7

CLOCK

OUTPUT

B

2 1

A

DISABLE

V

16

DD

R

15

D0

14

D1

13

D2

125 11

D3

10

B

DATA

}

DISABLE

9

A

Q0

3

4

Q1

5

Q2

Q3

6

= PIN 16

V

DD

V

= PIN 8

SS

FUNCTION TABLE

Inputs

Data Disable

Reset Clock

1 X X X X 0 0 0 X X X Q 0 1 X X Q 0 X 1 X Q 0 0 0 0 0 0 0 0 1 1

When either output disable A or B (or both) is (are) high the output is disabled to the high–impedance state; however sequential operation of the flip–flops is not affected. X = Don’t Care.

A B

Data Output

D

Q

n n n

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2

MC14076B

V

DD

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Output Voltage “0” Level

= VDD or 0

V

in

ОООООООО

“1” Level

V

= 0 or V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

ОООООООО

(V

OH

DD

= 4.5 or 0.5 Vdc) = 9.0 or 1.0 Vdc) = 13.5 or 1.5 Vdc)

“1” Level = 0.5 or 4.5 Vdc) = 1.0 or 9.0 Vdc) = 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source = 4.6 Vdc) = 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

= 50 pF on all outputs, all

(C

L

ОООООООО

buffers switching)

(4.) (5.)

Three–State Leakage Current

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

ÎÎ

V

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

ÎÎ

I

DD

ÎÎ

I

ÎÎ

I

TL

Vdc

5.0 10

Î

15

5.0 10

Î

15

IL

Î

5.0 10

Î

15

IH

Î

5.0 10

Î

15

Î

5.0

Î

10

Î

15

5.0 10

Î

15 15

in

—

Î

5.0 10

Î

15

T

5.0

Î

10 15

Î

15

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2 — —

Î

— —

Î

—

ООООООООООООООО

—

SS

– 55_C

)

Max

0.05

Î

0.05 —

—

Î

—

Î

1.5

3.0

Î

4.0

Î

— —

Î

—

Î

— —

Î

—

Î

— —

—

Î

—

± 0.1

—

Î

5.0 10

Î

20

± 0.1

25_C

Min

— —

ÎÎ

—

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

ÎÎ

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4 — —

ÎÎ

— —

ÎÎ

—

(3.)

Typ

0 0

Î

0

5.0 10

Î

15

Î

2.25

4.50

Î

6.75

Î

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

– 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.005

0.010

Î

0.015

IT = (0.75 µA/kHz) f + I IT = (1.50 µA/kHz) f + I IT = (2.25 µA/kHz) f + I

—

± 0.0001

Max

0.05

ÎÎ

0.05 —

—

ÎÎ

—

ÎÎ

1.5

3.0

ÎÎ

4.0

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

—

ÎÎ

—

± 0.1

7.5

ÎÎ

5.0 10

ÎÎ

20

DD DD DD

± 0.1

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 1.7

– 0.36

Î

– 0.9

Î

– 2.4

0.36

0.9

Î

2.4 — —

Î

— —

Î

—

125_C

Max

0.05

Î

0.05

Î

± 1.0

Î

± 3.0

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

T

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

150 300 600

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

µAdc

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3

MC14076B

Î

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(6.)

(C

= 50 pF, T

L

Output Rise and Fall Time

t

, t

TLH

t

ООООООООООООО

TLH

t

TLH

Propagation Delay Time

ООООООООООООО

Clock to Q

ООООООООООООО

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

, t

t t t

PLH PLH PLH

= (1.7 ns/pF) CL + 215 ns

PHL

, t

= (0.66 ns/pF) CL + 92 ns

PHL

, t

= (0.5 ns/pF) CL + 65 ns

PHL

= 25_C)

A

Symbol

ÎÎÎ

t

, t

TLH

ÎÎÎ

t

, t

PLH

ÎÎÎ

THL

PHL

V

DD

Vdc

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

Min

ÎÎ

— —

ÎÎ

—

ÎÎ

—

ÎÎ

—

ÎÎ

—

(7.)

Typ

ÎÎ

100

50

ÎÎ

40

ÎÎ

300

ÎÎ

125

ÎÎ

90

Max

ÎÎ

200 100

ÎÎ

80

ÎÎ

600

ÎÎ

250

ÎÎ

180

Reset to Q

t

, t

PLH

ООООООООООООО

t

PLH

ООООООООООООО

t

PLH

= (1.7 ns/pF) CL + 215 ns

PHL

, t

= (0.66 ns/pF) CL + 92 ns

PHL

, t

= (0.5 ns/pF) CL + 65 ns

PHL

3–State Propagation Delay, Output “1” or “0”

to High Impedance

ООООООООООООО

3–State Propagation Delay, High Impedance

ООООООООООООО

to “1” or “0” Level

ООООООООООООО

Clock Pulse Width

ООООООООООООО

Reset Pulse Width

ООООООООООООО

Data Setup Time

ООООООООООООО

Data Hold Time

ООООООООООООО

Data Disable Setup Time

ООООООООООООО

Clock Pulse Rise and Fall Time

ООООООООООООО

Clock Pulse Frequency

ООООООООООООО

ÎÎÎ

t

, t

PHZ

PLZ

ÎÎÎ

t

, t

PZH

PZL

ÎÎÎ

t

WH

ÎÎÎ

t

WH

ÎÎÎ

t

su

ÎÎÎ

t

h

ÎÎÎ

t

su

ÎÎÎ

t

, t

TLH

THL

ÎÎÎ

f

cl

ÎÎÎ

5.0

ÎÎ

10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10 15

ÎÎ

—

ÎÎ

—

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

260 110

ÎÎ

80

370 150

ÎÎ

110

30

ÎÎ

10

4

ÎÎ

130

60

ÎÎ

50

220

80

ÎÎ

50 —

ÎÎ

— —

ÎÎ

— — —

ÎÎ

300

ÎÎ

125

ÎÎ

90

150

60

ÎÎ

45

200

ÎÎ

80 60

ÎÎ

130

55

ÎÎ

40

185

75

ÎÎ

55 15

ÎÎ

5 2

ÎÎ

65 30

ÎÎ

25

110

40

ÎÎ

25 —

ÎÎ

— —

ÎÎ

3.6

9.0 12

ÎÎ

600

ÎÎ

250

ÎÎ

180 300

120

ÎÎ

90

400

ÎÎ

160 120

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

— 15

ÎÎ

5 4

ÎÎ

1.8

4.5

6.0

ÎÎ

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

µs

Î

MHz

Î

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4

MC14076B

20

INPUT

D

INFORMATION

Q OUTPUT

INPUT RISE AND FALL 20 ns

90%

50%

10%

t

su

h

50%

t

WH

f

t

PLH

10%

t

TLH

cl

90%

RESET = 0 DATA DISABLE A AND B = 0 OUTPUT DISABLE A AND B = 0

Figure 1. Timing Diagram

OUTPUT DISABLE A OUTPUT DISABLE B

OUTPUT DISABLE

A OR B

V

DD

V

h

50%

t

PHL

SS

V

DD

V

SS

V

OH

V

OL

t

su

t

20 ns

90%

t

WL

t

THL

10%

ANY Q

OUTPUT

ANY Q

OUTPUT

OUTPUTS

CONNECTED

OTHER INPUTS

50%

ns

t

PLZ

10%

t

PHZ

90%

MC14076B

90%

50%

OUTPUTS

DISCONNECTED

OUTPUT DISABLE

10%

90%

10%

ANY Q

OUTPUT

R

= 1 kΩ

L

C

L

ns

t

PZL

t

PZH

V

DD

V

SS

V

OH

≈ 2.5 V @ V

≈ 2 V @ VDD = 5 V ≈ 6 V @ V ≈ 10 V @ V

V

OL

DD

10 V, AND 15 V

= 10 V

DD

= 5 V,

= 15 V

OUTPUTS

CONNECTED

VDD FOR t VSS FOR t

PLZ

PHZ

AND t

PZL PZH

A OR B

Figure 2. Three–State Propagation Delay

Waveshape and Circuit

EQUIVALENT

FUNCTIONAL BLOCK DIAGRAM

1 2

D0

DATA DISABLE A DATA DISABLE B910

D1 13

CLOCK 7

D2 12

D3 11

RESET 15

14

DQ

C

Q

R

3Q0

DQ

C

Q

R

4Q1

DQ

C

Q

R

DQ

C

Q

R

5Q2

6Q3

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5

P ACKAGE DIMENSIONS

PLASTIC DIP PACKAGE

–A–

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

C

S

SEATING

–T–

PLANE

K

M

A

MC14076B

PDIP–16

P SUFFIX

CASE 648–08

ISSUE R

J

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

M

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53

F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES

____

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6

–T–

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14076B

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

F

J

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

____

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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7

MC14076B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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8

MC14076B/D

Datasheet MC14076BD, MC14076BDR2, MC14076BCP Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual