Datasheet MC14077BD, MC14077BDR2, MC14077BF, MC14077BFEL, MC14077BCP Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14070B/D

MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

• MC14070B — Replacement for CD4030B and CD4070B Types

• MC14077B — Replacement for CD4077B Type

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC140XXBCP PDIP–14 2000/Box
MC140XXBD SOIC–14

2750/Box
MC140XXBDR2 SOIC–14 2500/Tape & Reel
MC140XXBF SOEIAJ–14 See Note 1.

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC140XXBCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

140XXB

AWLYWW

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC140XXB

AWLYWW

MC140XXBFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

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2

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

C

OUT

D

IN 1

D

IN 2

D

V

DD

IN 1

C

IN 2

C

OUT

B

OUT

A

IN 2

A

IN 1

A

V

SS

IN 2

B

IN 1

B

Figure 1. Power Dissipation Test Circuit and Waveform

V

DD

V

in

C

L

*

I

DD

20 ns 20 ns

V

DD

V

SS

90%

50%

10%

V

in

1/f

50% DUTY CYCLE

*Inverted output on MC14077B only.

Figure 2. Switching Time Test Circuit and Waveforms

V

DD

C

L

20 ns

V

SS

V

SS

90%

OUTPUT

#

*

20 ns

V

OH

V

OL

V

DD

t

THL

t

TLH

50%

10%

90%

50%

10%

t

PLH

t

PHL

INPUT

*Inverted output on MC14077B only.

PULSE

GENERATOR

#Connect unused input to V

DD

for MC14070B, to VSS for MC14077B.

MC14070B

QUAD Exclusive OR

Gate

MC14077B

QUAD Exclusive NOR

Gate

13

11

12

9

8

6

5

2

1

10

4

3

13

12

9

8

6

5

2

1

11

10

4

3

V

DD

= PIN 14

V

SS

= PIN 7

(BOTH DEVICES)

MC14070B, MC14077B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ООООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

—
—
—

ÎÎ

Î

0
0
0

Î

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ООООООООО

Î

“1” Level

V

in

= 0 or V

DD

ÎÎ

Î

V

OH

5.0
10
15

ÎÎ

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

4.95

9.95

14.95

ÎÎ

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

2.25

4.50

6.75

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

5.0
10
15

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

ÎÎ

Î

ÎÎ

Î

2.75

5.50

8.25

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

ООООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

OH

5.0

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 2.4

– 0.51

– 1.3
– 3.4

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 4.2
– 0.88
– 2.25

– 8.8

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

mAdc

ООООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

I

OL

5.0
10
15

ÎÎ

Î

0.64

1.6

4.2

Î

Î

—
—
—

Î

Î

0.51

1.3

3.4

ÎÎ

Î

0.88

2.25

8.8

Î

Î

—
—
—

Î

Î

0.36

0.9

2.4

Î

Î

—
—
—

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ООООООООО

Î

Input Capacitance

(V

in

= 0)

ÎÎ

Î

C

in

—

ÎÎ

Î

—

Î

Î

—

Î

Î

—

ÎÎ

Î

5.0

Î

Î

7.5

Î

Î

—

Î

Î

—

Î

Î

pF

ООООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

I

DD

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

0.25

0.5

1.0

Î

Î

—
—
—

ÎÎ

Î

0.0005

0.0010

0.0015

Î

Î

0.25

0.5

1.0

Î

Î

—
—
—

Î

Î

7.5
15
30

Î

Î

µAdc

ООООООООО

Î

ООООООООО

Î

ООООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

T

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.3 µA/kHz) f + I

DD

IT = (0.6 µA/kHz) f + I

DD

IT = (0.9 µA/kHz) f + I

DD

Î

Î

Î

Î

Î

Î

µAdc

ООООООООО

Î

ООООООООО

Î

ООООООООО

Î

Output Rise and Fall Times

(5.)

(CL = 50 pF)

t

TLH

, t

THL

= (1.35 ns/pF) CL + 33 ns

t

TLH

, t

THL

= (0.60 ns/pF) CL + 20 ns

t

TLH

, t

THL

= (0.40 ns/pF) CL + 20 ns

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

t

TLH

,

t

THL

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

100

50
40

Î

Î

Î

Î

Î

Î

200
100

80

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

ns

ООООООООО

Î

ООООООООО

Î

Propagation Delay Times

(5.)

(CL = 50 pF)

t

PLH

, t

PHL

= (0.90 ns/pF) CL + 130ns

t

PLH

, t

PHL

= (0.36 ns/pF) CL + 57 ns

t

PLH

, t

PHL

= (0.26 ns/pF) CL + 37 ns

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

175

75
55

Î

Î

Î

Î

350
150
110

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

ns

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14070B, MC14077B

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4

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14070B, MC14077B

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5

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

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6

P ACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L
DETAIL P

M

A

b
c
D
E
e

0.50

M

Z

MC14070B, MC14077B

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7

Notes

MC14070B, MC14077B

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8

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specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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