Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14067B MC14097B
Analog
Multiplexers/Demultiplexers
The MC14067 and MC14097 multiplexers/demultiplexers are digitally
controlled analog switches f eaturing low ON r esistance and very low
leakage current. These devices can be used in either digital or analog
applications.
The MC14067 is a 16–channel multiplexer/demultiplexer with an inhibit
and four binary control inputs A, B, C, and D. These control inputs select
1–of–16 channels by turning O N the appropriate analog switch (see
MC14067 truth table.)
The MC14097 is a differential 8–channel multiplexer/demultiplexer with an
inhibit and three binary control inputs A, B, and C. These control inputs
select 1 of 8 pairs of channels by turning ON the appropriate analog switches
(see MC14097 truth table).
• Low OFF Leakage Current
• Matched Channel Resistance
• Low Quiescent Power Consumption
• Low Crosstalk Between Channels
• Wide Operating Voltage Range: 3 to 18 V
• Low Noise
• Pin for Pin Replacement for CD4067B and CD4097B
MC14067B
16–Channel Analog
Multiplexer/Demultiplexer
MC14097B
Dual 8–Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
COMMON
OUT/IN
16
17
18
19
21
22
23
2
3
4
5
6
7
9
13
8
14
11
10
15
20
1
INHIBIT
A
B
C
D
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X
CONTROLS
SWITCHES
IN/OUT
COMMONS
OUT/IN
1
17
15
16
18
19
21
22
23
2
3
4
5
6
7
9
8
14
11
10
1320INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
Y
VDD = PIN 24
VSS = PIN 12
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14067B
MC14097B
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
Page 2
MOTOROLA CMOS LOGIC DATAMC14067B MC14097B
2
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
I
in
Input Current (DC or Transient),
per Control Pin
± 10
mA
I
sw
Switch Through Current
± 25
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14067 TRUTH TABLE
Control Inputs
Selected
A B C D Inh
Selected
Channel
X X X X 1 None
0 0 0 0 0 X0
1 0 0 0 0 X1
0 1 0 0 0 X2
1 1 0 0 0 X3
0 0 1 0 0 X4
1 0 1 0 0 X5
0 1 1 0 0 X6
1 1 1 0 0 X7
0 0 0 1 0 X8
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15
MC14097 TRUTH TABLE
Control Inputs
Selected
A B C Inh
Selected
Channels
X X X 1 None
0 0 0 0 X0 Y0
1 0 0 0 X1 Y1
0 1 0 0 X2 Y2
1 1 0 0 X3 Y3
0 0 1 0 X4 Y4
1 0 1 0 X5 Y5
0 1 1 0 X6 Y6
1 1 1 0 X7 Y7
X = Don’t Care
MC14067 FUNCTIONAL DIAGRAM MC14097 FUNCTIONAL DIAGRAM
1–OF–16 DECODER
INHIBIT
A
B
C
D
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
CONTROL
INPUTS
X
IN/OUT
X
OUT/IN
INHIBIT
A
B
C
CONTROL
INPUTS
1–OF–8 DECODER
X7
X6
X5
X4
X3
X2
X1
X0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
X
OUT/IN
Y
OUT/IN
X
IN/OUT
Y
IN/OUT
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14067B MC14097B
ELECTRICAL CHARACTERISTICS
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
– 55°C
25_C
125_C
Characteristic
Symbol
VDDTest Conditions
ÎÎ
ÎÎ
ÎÎ
Min
Max
Min
Typ #
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
Power Supply Voltage
Range
V
DD
—
3.0
18
3.0
—
18
3.0
18
V
Quiescent Current Per
Package
I
DD
5.0
10
15
Control Inputs: Vin
=
VSS or VDD,
Switch I/O: VSS v V
I/O
v
VDD, and
∆V
switch
v
500 mV**
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µA
Total Supply Current
(Dynamic Plus
Quiescent,
Per Package
I
D(AV)
5.0
10
15
TA = 25_C only (The
channel component,
(Vin – V
out
)/Ron, is
not included.)
(0.07 µA/kHz) f + I
DD
Typical (0.20 µA/kHz) f + I
DD
(0.36 µA/kHz) f + I
DD
µA
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)
Low–Level Input Voltage
V
IL
5.0
10
15
Ron = per spec,
I
off
= per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
High–Level Input Voltage
V
IH
5.0
10
15
Ron = per spec,
I
off
= per spec
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
V
Input Leakage Current
I
in
15
Vin = 0 or V
DD
—
± 0.1
—
±0.00001
± 0.1
—
1.0
µA
Input Capacitance
C
in
—
—
—
—
5.0
7.5
—
—
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)
Recommended Peak–to–
Peak Voltage Into or
Out of the Switch
V
I/O
—
Channel On or Off
0
V
DD
0
—
V
DD
0
V
DDVp–p
Recommended Static or
Dynamic Voltage
Across the Switch’*
(Figure 1)
∆V
switch
—
Channel On
0
600
0
—
600
0
300
mV
Output Offset Voltage
V
OO
—
Vin = 0 V, No Load
—
—
—
10
—
—
—
µV
ON Resistance
R
on
5.0
10
15
∆V
switch
v 500 mV**,
Vin = VIL or V
IH
(Control), and V
in
0 to VDD (Switch)
—
—
—
800
400
220
—
—
—
250
120
80
1050
500
280
—
—
—
1300
550
320
Ω
∆ON Resistance Between
Any Two Channels
in the Same Package
∆R
on
5.0
10
15
—
—
—
70
50
45
—
—
—
25
10
10
70
50
45
—
—
—
135
95
65
Ω
Off–Channel Leakage
Current (Figure 2)
I
off
15
Vin = VIL or V
IH
(Control) Channel to
Channel or Any One
Channel
—
± 100
—
± 0.05
± 100
—
±1000
nA
Capacitance, Switch I/O
C
I/O
—
Inhibit = V
DD
—
—
—
10
—
—
—
pF
Capacitance, Common O/I
C
O/I
—
Inhibit = V
DD
(MC14067B)
(MC14097B)
———
—
—
—
100
60
—
—
———
—
pF
Capacitance, Feedthrough
(Channel Off)
C
I/O
——Pins Not Adjacent
Pins Adjacent
—
—
—
0.47
—
—
—
pF
Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
**For voltage drops across the switch (∆V
switch
) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
Page 4
MOTOROLA CMOS LOGIC DATAMC14067B MC14097B
4
ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol
VDD – V
SS
Vdc
Typ #
Max
Unit
Propagation Delay Times
Channel Input–to–Channel Output (RL = 200 kΩ)
MC14067B
t
PLH,tPHL
(Figure 3)
5.0
10
15
35
15
12
90
40
30
ns
MC14097B
5.0
10
15
25
10
7
65
25
18
ns
Control Input–to–Channel Output
Channel Turn–On Time (RL = 10 kΩ)
MC14067B/097B
t
PZH
, t
PZL
(Figure 4)
5.0
10
15
240
115
75
600
290
190
ns
Channel Turn–Off Time (RL = 300 kΩ)
MC14067B/097B
t
PHZ,tPLZ
(Figure 4)
5.0
10
15
250
120
75
625
300
190
ns
Any Pair of Address Inputs to Output
MC14067B
t
PLH
, t
PHL
5.0
10
15
280
115
85
700
290
215
ns
MC14097B
(Figure 10)
5.0
10
15
250
100
75
625
250
190
ns
Second Harmonic Distortion
(RL = 10 kΩ, f = 1 kHz, Vin = 5 V
p–p
)
—
10
0.3
—
%
ON Channel Bandwidth
[RL = 1 kΩ, Vin = 1/2 (VDD – VSS)
p–p
(sine–wave)]
20 Log10 (V
out/Vin
) = – 3 dB MC14067B
MC14097B
BW
(Figure 5)
10
10
15
25
—
—
MHz
Off Channel Feedthrough Attenuation
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS)
p–p
(sine–wave)]
fin = 20 MHz – MC14067B
fin = 12 MHz – MC14097B
—
(Figure 5)
10
– 40
—
dB
Channel Separation
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS)
p–p
(sine–wave)]
fin = 20 MHz—(Figure 6)
10
– 40
—
dB
Crosstalk, Control Inputs–to–Common O/I
(R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns, Inhibit = VSS)
—
(Figure 7)
10
30
—
mV
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14067B MC14097B
Figure 1. ∆V Across Switch Figure 2. Off Channel Leakage
CONTROL
SECTION
OF IC
SOURCE
V
LOAD
ON SWITCH
CONTROL
SECTION
OF IC
OFF CHANNEL UNDER TEST
OTHER
CHANNEL(S)
V
DD
V
SS
V
SS
V
DD
V
SS
V
DD
A
X3
X5
X6
X7
X
X1
X2
X4 X11
X10
X9
X8
V
DD
INHIBIT
X15
X14
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
D
C
X13
X12
B
V
SS
A
X0
MC14067B
PIN ASSIGNMENT
MC14097B
PIN ASSIGNMENT
X3
X5
X6
X7
X
X1
X2
X4 Y3
Y2
Y1
Y0
V
DD
Y7
Y6
Y
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
INHIBIT
C
Y5
Y4
B
V
SS
A
X0
Page 6
MOTOROLA CMOS LOGIC DATAMC14067B MC14097B
6
Figure 3. Propagation Delay Test Circuit
and Waveforms Vin to V
out
Figure 4. Turn–On and Delay Turn–Off
Test Circuit and Waveforms
V
DD
V
out
CL = 50 pF
R
L
V
in
A
B
C
D
INH
V
in
V
out
20 ns
20 ns
V
DD
V
SS
50%
10%
t
PLH
t
PHL
90%
50%
PULSE
GENERATOR
V
C
A
B
C
D
INH
R
L
CL = 50 pF
V
out
V
in
VDDVSSVSSV
DD
V
X
20 ns 20 ns
90%
50%
10%
90%
10%
V
out
V
out
V
C
50%
50%
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Vin = V
DD
VX = V
SS
Vin = V
SS
VX = V
DD
Figure 5. Bandwidth and Off–Channel
Feedthrough Attenuation
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
A, B, and C inputs used to turn ON or OFF
the switch under test.
A
B
C
D
INH
V
in
R
L
CL = 50 pF
V
out
V
DD
R
L
V
out
CL = 50 pF
R
L
V
in
A
B
C
D
INH
OFF
ON
Figure 7. Crosstalk, Control to Common O/I
V
C
A
B
C
D
INH
R
L
CL = 50 pF
V
out
R1
Page 7
MOTOROLA CMOS LOGIC DATA
7
MC14067B MC14097B
Figure 8. Channel Resistance (RON) Test Circuit
V
DD
V
SS
10 k
KEITHLEY 160
DIGITAL
MULTIMETER
X–Y
PLOTTER
1 k
Ω
RANGE
V
DD
V
A
V
B
A
B
C
D
INH
C
L
V
DD
V
out
V
out
V
B
V
A
50%
50%
t
PHL
t
PLH
50%
Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
TYPICAL RESISTANCE CHARACTERISTICS
Figure 10. VDD = 7.5 V, VSS = – 7.5 V Figure 11. VDD = 5.0 V, VSS = – 5.0 V
R
ON
, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
–55°C
R
ON
, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
–55°C
Figure 12. VDD = 2.5 V, VSS = – 2.5 V
R
ON
, “ON” RESISTANCE (OHMS)
700
600
500
400
300
200
0
100
–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
–55°C
Figure 13. Comparison at 25°C, VDD = –V
SS
R
ON
, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 25°C
VDD = 2.5 V
5.0 V
7.5 V
Page 8
MOTOROLA CMOS LOGIC DATAMC14067B MC14097B
8
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Multiplexer/Demultiplexer. The 0–to–5 volt Digital Control signal is used to
directly control a 5 V
p–p
analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example. VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by V
DD
and VSS. The analog voltage must swing neither higher than
VDD nor lower than VSS. The example shows a 5 V
p–p
signal
which allows no margin at either peak. If voltage transients
above VDD and/or below VSS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between V
DD
and VSS is 18.0 volts. Most parameters are specified up to
15 V w hich i s the recommended m aximum d ifference
between VDD and VSS.
Figure A. Application Example
+5 V
V
DD
V
SS
5 V
p–p
ANALOG SIGNAL
0–TO–5 V DIGITAL
CONTROL SIGNALS
SWITCH
I/O
MC14067B
MC14097B
COMMON
O/I
5 V
p–p
ANALOG SIGNAL
+5.0 V
+
2.5 V
GND
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
Figure B. External Germanium or Schottky Clipping Diodes
V
DD
V
DD
V
SS
V
SS
D
X
D
X
D
X
D
X
SWITCH
I/O
COMMON
O/I
Page 9
MOTOROLA CMOS LOGIC DATA
9
MC14067B MC14097B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 31.37 32.13 1.235 1.265
B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
J 0.20 0.38 0.008 0.015
K 2.92 3.43 0.115 0.135
L 15.24 BSC 0.600 BSC
M 0 15 0 15
N 0.51 1.02 0.020 0.040
_ _ _ _
1 12
1324
B
H
A
F
D
G
K
SEATING
PLANE
N
C
M
J
L
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
1 12
24 13
B
A
SEATING
PLANE
F
D
G
K
N
C
M
J
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 31.24 32.77 1.230 1.290
B 12.70 15.49 0.500 0.610
C 4.06 5.59 0.160 0.220
D 0.41 0.51 0.016 0.020
F 1.27 1.52 0.050 0.060
G 2.54 BSC 0.100 BSC
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 15.24 BSC 0.600 BSC
M 0 15 0 15
N 0.51 1.27 0.020 0.050
_ _ _ _
Page 10
MOTOROLA CMOS LOGIC DATAMC14067B MC14097B
10
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B
M
S
A
M
0.010 (0.25) B
S
T
–T–
G
22X
SEATING
PLANE
K
C
R
X 45
_
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 15.25 15.54 0.601 0.612
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
M 0 8 0 8
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
____
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USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
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and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer .
MC14067B/D
*MC14067B/D*
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