Datasheet MC14066BD, MC14066BDR2, MC14066BDT, MC14066BDTEL, MC14066BCP Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14066B/D

MC14066B

Quad Analog Switch/Quad
Multiplexer

The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.

The MC14066B is designed to be pin–for–pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.

• Triple Diode Protection on All Control Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linearized Transfer Characteristics

• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical

• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B

• For Lower R

ON

, Use The HC4066 High–Speed CMOS Device

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

I

in

Input Current (DC or Transient)

per Control Pin

±10 mA

I

SW

Switch Through Current ±25 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14066BCP PDIP–14 2000/Box
MC14066BD SOIC–14

55/Rail
MC14066BDR2 SOIC–14 2500/Tape & Reel
MC14066BDT TSSOP–14

MC14066BF SOEIAJ–14

96/Rail

See Note 1.

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14066BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14
DT SUFFIX

CASE 948G

1

14

14066B

AWLYWW

14

066B

ALYW

1

14

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14066B

AWLYWW

MC14066BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

MC14066BDTR2 TSSOP–14 2500/Tape & Reel

MC14066BDTEL TSSOP–14 2000/Tape & Reel

MC14066B

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2

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 4

IN 4

CONTROL 4

CONTROL 1

V

DD

IN 3

OUT 3

IN 2

OUT 2

OUT 1

IN 1

V

SS

CONTROL 3

CONTROL 2

LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)

BLOCK DIAGRAM

IN/OUT

CONTROL

OUT/IN

IN 4

CONTROL 4

IN 3

CONTROL 3

IN 2

CONTROL 2

IN 1

CONTROL 1

OUT 1

OUT 2

OUT 3

OUT 4

13

1
5

4
6

8

12

11

2

3

9

10

V

DD

= PIN 14

V

SS

= PIN 7

Control Switch

0=V

SS

OFF

1=VDDON

Logic Diagram Restrictions

VSS ≤ Vin ≤ V

DD

VSS ≤ V

out

≤ V

DD

CIRCUIT SCHEMATIC

(1/4 OF CIRCUIT SHOWN)

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

300 Ω

CMOS
INPUT

MC14066B

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3

ELECTRICAL CHARACTERISTICS

–55_C

25_C

125_C

Characteristic

Symbol

V

DD

Test Conditions

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

V

DD

—

3.0

18

3.0

—

18

3.0

18

V

ОООООО

Î

ОООООО

Î

ОООООО

Î

Quiescent Current Per

Package

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

DD

5.0
10
15

ООООО

Î

ООООО

Î

ООООО

Î

Control Inputs:

V

in

= VSS or VDD,

Switch I/O: V

SS

v V

I/O

v

VDD, and

∆V

switch

v 500 mV

(5.)

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

0.25

0.5

1.0

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

0.005

0.010

0.015

Î

Î

Î

Î

Î

Î

0.25

0.5

1.0

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

7.5
15
30

µA

ОООООО

Î

ОООООО

Î

Total Supply Current

(Dynamic Plus Quiescent,
Per Package

ÎÎ

Î

ÎÎ

Î

I

D(AV)

5.0
10
15

ООООО

Î

ООООО

Î

TA = 25_C only The

channel component,
(V

in

– V

out

)/Ron, is

not included.)

ООООООООООООО

Î

ООООООООООООО

Î

(0.07 µA/kHz) f + I

DD

Typical (0.20 µA/kHz) f + I

DD

(0.36 µA/kHz) f + I

DD

µA

CONTROL INPUTS (Voltages Referenced to VSS)

ОООООО

Î

Low–Level Input Voltage

ÎÎ

Î

V

IL

5.0
10
15

ООООО

Î

Ron = per spec,
I

off

= per spec

Î

Î

—
—
—

Î

Î

1.5

3.0

4.0

—
—
—

ÎÎ

Î

2.25

4.50

6.75

Î

Î

1.5

3.0

4.0

Î

Î

—
—
—

Î

Î

1.5

3.0

4.0

V

ОООООО

Î

ОООООО

Î

High–Level Input Voltage

ÎÎ

Î

ÎÎ

Î

V

IH

5.0
10
15

ООООО

Î

ООООО

Î

Ron = per spec,
I

off

= per spec

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

3.5

7.0
11

ÎÎ

Î

ÎÎ

Î

2.75

5.50

8.25

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

V

Input Leakage Current

I

in

15

Vin = 0 or V

DD

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µA

Input Capacitance

C

in

—

—

—

—

5.0

7.5

—

—

pF

SWITCHES IN AND OUT (Voltages Referenced to VSS)

ОООООО

Î

ОООООО

Î

Recommended Peak–to–

Peak Voltage Into or Out
of the Switch

ÎÎ

Î

ÎÎ

Î

V

I/O

—

ООООО

Î

ООООО

Î

Channel On or Off

Î

Î

Î

Î

0

Î

Î

Î

Î

V

DD

0

ÎÎ

Î

ÎÎ

Î

—

Î

Î

Î

Î

V

DD

Î

Î

Î

Î

0

Î

Î

Î

Î

V

DDVp–p

ОООООО

Î

Recommended Static or

Dynamic Voltage Across
the Switch (5.) (Figure 1)

ÎÎ

Î

∆V

switch

—

ООООО

Î

Channel On

Î

Î

0

Î

Î

600

0

ÎÎ

Î

—

Î

Î

600

Î

Î

0

Î

Î

300

mV

Output Offset Voltage

V

OO

—

Vin = 0 V, No Load

—

—

—

10

—

—

—

µV

ОООООО

Î

ОООООО

Î

ON Resistance

ÎÎ

Î

ÎÎ

Î

R

on

5.0
10
15

ООООО

Î

ООООО

Î

∆V

switch

v 500 mV

(5.)

,

V

in

= VIL or V

IH

(Control), and Vin =
0 to V

DD

(Switch)

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

800
400
220

—
—
—

ÎÎ

Î

ÎÎ

Î

250
120

80

Î

Î

Î

Î

1050

500
280

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1200

520
300

Ω

ОООООО

Î

∆ON Resistance Between

Any Two Channels
in the Same Package

ÎÎ

Î

∆R

on

5.0
10
15

ОООООÎÎ

Î

—
—
—

Î

Î

70
50
45

—
—
—

ÎÎ

Î

25
10
10

Î

Î

70
50
45

Î

Î

—
—
—

Î

Î

135

95
65

Ω

ОООООО

Î

ОООООО

Î

Off–Channel Leakage

Current (Figure 6)

ÎÎ

Î

ÎÎ

Î

I

off

15

ООООО

Î

ООООО

Î

Vin = VIL or V

IH

(Control) Channel to
Channel or Any One
Channel

Î

Î

Î

Î

—

Î

Î

Î

Î

±100

—

ÎÎ

Î

ÎÎ

Î

± 0.05

Î

Î

Î

Î

±100

Î

Î

Î

Î

—

Î

Î

Î

Î

±1000

nA

Capacitance, Switch I/O

C

I/O

—

Switch Off

—

—

—

10

15

—

—

pF

ОООООО

Î

Capacitance, Feedthrough

(Switch Off)

ÎÎ

Î

C

I/O

—
—

ОООООÎÎ

Î

—

Î

Î

—

—

ÎÎ

Î

0.47

Î

Î

—

Î

Î

—

Î

Î

—

pF

4. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

5. For voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the

current out of the switch may contain both V

DD

and switch input components. The reliability of the device will be unaffected unless the

Maximum Ratings are exceeded. (See first page of this data sheet.)

MC14066B

http://onsemi.com

4

ELECTRICAL CHARACTERISTICS

(6.)

(C

L

= 50 pF, TA = 25_C unless otherwise noted.)

Characteristic

Symbol

V

DD

Vdc

Min

Typ

(7.)

Max

Unit

ОООООООООООООО

Î

ОООООООООООООО

Î

ОООООООООООООО

Î

Propagation Delay Times V

SS

= 0 Vdc

Input to Output (R

L

= 10 kΩ)

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 15.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 6.0 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 4.0 ns

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

t

PLH

, t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

20
10

7.0

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

40
20
15

Î

Î

Î

Î

Î

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

Control to Output (RL = 1 kΩ) (Figure 2)

Output “1” to High Impedance

ÎÎ

Î

ÎÎ

Î

t

PHZ

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

40
35
30

ÎÎ

Î

ÎÎ

Î

80
70
60

Î

Î

Î

Î

ns

ОООООООООООООО

Î

Output “0” to High Impedance

ÎÎ

Î

t

PLZ

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

40
35
30

ÎÎ

Î

80
70
60

Î

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

High Impedance to Output “1”

ÎÎ

Î

ÎÎ

Î

t

PZH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

60
20
15

ÎÎ

Î

ÎÎ

Î

120

40
30

Î

Î

Î

Î

ns

ОООООООООООООО

Î

High Impedance to Output “0”

ÎÎ

Î

t

PZL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

60
20
15

ÎÎ

Î

120

40
30

Î

Î

ns

ОООООООООООООО

Î

Second Harmonic Distortion VSS = – 5 Vdc

(V

in

= 1.77 Vdc, RMS Centered @ 0.0 Vdc,

R

L

= 10 kΩ, f = 1.0 kHz)

ÎÎ

Î

—

ÎÎ

Î

5.0

ÎÎ

Î

—

ÎÎ

Î

0.1

ÎÎ

Î

—

Î

Î

%

ОООООООООООООО

Î

ОООООООООООООО

Î

Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc

(R

L

= 1 kΩ, 20 Log (V

out/Vin

) = – 3 dB, CL = 50 pF,

V

in

= 5 V

p–p

)

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

5.0

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

65

ÎÎ

Î

ÎÎ

Î

—

Î

Î

Î

Î

MHz

Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc

(V

in

= 5 V

p–p

, RL = 1 kΩ, fin = 1.0 MHz) (Figure 3)

—

5.0

—

– 50

—

dB

ОООООООООООООО

Î

ОООООООООООООО

Î

Channel Separation (Figure 4) VSS = – 5 Vdc

(V

in

= 5 V

p–p

, RL = 1 kΩ, f

in

= 8.0 MHz)

(Switch A ON, Switch B OFF)

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

5.0

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

– 50

ÎÎ

Î

ÎÎ

Î

—

Î

Î

Î

Î

dB

ОООООООООООООО

Î

Crosstalk, Control Input to Signal Output (Figure 5)

V

SS

= – 5 Vdc

(R

1

= 1 kΩ, RL = 10 kΩ, Control t

TLH

= t

THL

= 20 ns)

ÎÎ

Î

—

ÎÎ

Î

5.0

ÎÎ

Î

—

ÎÎ

Î

300

ÎÎ

Î

—

Î

Î

mV

p–p

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14066B

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5

TEST CIRCUITS

Figure 1. ∆V Across Switch Figure 2. Turn–On Delay Time Test Circuit

and Waveforms

Figure 3. Bandwidth and

Feedthrough Attenuation

Figure 4. Channel Separation

Figure 5. Crosstalk,

Control to Output

Figure 6. Off Channel Leakage

CONTROL

SECTION

OF IC

SOURCE

V

LOAD

ON SWITCH

V

out

V

out

V

C

V

C

V

out

V

in

R

L

C

L

20 ns

V

DD

V

SS

90%

50%

10%

t

PZH

t

PHZ

t

PZL

t

PLZ

10%

90%

10%

V

x

V

out

C

L

R

L

VDDV

SS

V

C

V

in

VDD – V

SS

2

V

DD

– V

SS

2

V

in

V

DD

V

SS

R

L

C

L

R

L

C

L

V

in

1 k

V

out

R

L

CL = 50 pF

V

C

= –5.0 V TO +5.0 V SWING

VC = VDD FOR BANDWIDTH TEST
V

C

= VSS FOR FEEDTHROUGH TEST

OFF CHANNEL UNDER TEST

V

DD

V

SS

V

SS

V

DD

A

CONTROL

SECTION

OF IC

90%

V

in

= V

DD

Vx = V

SS

Vin = V

SS

Vx = V

DD

10 k

MC14066B

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6

Figure 7. Channel Resistance (RON) Test Circuit

V

DD

V

SS

10 k

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

1 kΩ

RANGE

X–Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

Figure 8. V

DD

= 7.5 V, VSS = – 7.5 V Figure 9. VDD = 5.0 V, VSS = – 5.0 V

R

ON

, “

O

N” R

ES

I

STA

NC

E

(

O

H

MS

)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

Figure 10. VDD = 2.5 V, VSS = – 2.5 V

R

ON

, “

O

N” R

ES

I

STA

NC

E

(

O

H

MS

)

700
600

500

400

300

200

0

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

Figure 11. Comparison at 25°C, VDD = –V

SS

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 25°C

VDD = 2.5 V

5.0 V

7.5 V

MC14066B

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7

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–
to–5 volt digital control signal is used to directly control a
5 volt peak–to–peak analog signal.

The digital control logic levels are determined by V

DD

and VSS. The VDD voltage is the logic high voltage, the V

SS

voltage is logic low . For the example, VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VSS. The analog voltage must not swing higher than
VDD or lower than VSS.

The example shows a 5 volt peak–to–peak signal which
allows no margin at either peak. If voltage transients above

V

DD

and/or below VSS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.

The absolute maximum potential difference between

V

DD

and VSS is 18.0 volts. Most parameters are specified up
to 15 volts which is the r ecommended maximum difference
between VDD and VSS.

Figure A. Application Example

+5 V

V

DD

V

SS

5 V

p–p

ANALOG SIGNAL

0–TO–5 V DIGITAL

CONTROL SIGNALS

SWITCH

IN

MC14066B

SWITCH

OUT

5 V

p–p

ANALOG SIGNAL

+5.0 V

+2.5 V

GND

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

Figure B. External Germanium or Schottky Clipping Diodes

V

DD

V

DD

V

SS

V

SS

D

X

D

X

D

X

D

X

SWITCH

IN

SWITCH

OUT

MC14066B

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8

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L

M ––– 10 ––– 10

N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14066B

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9

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC14066B

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10

P ACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

MC14066B

http://onsemi.com

11

P ACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L
DETAIL P

M

A

b
c
D
E
e

0.50

M

Z

MC14066B

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12

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