Datasheet MC14053BFR1, MC14053BFR2, MC14052BFR1, MC14052BFR2, MC14053BFL1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14051B/D

MC14051B, MC14052B,
MC14053B

Analog
Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.

• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (V

DD

– VEE) = 3.0 to 18 V

Note: VEE must be v V

SS

• Linearized Transfer Characteristics

• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical

• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

• For 4PDT Switch, See MC14551B

• For Lower R

ON

, Use the HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

MAXIMUM RATINGS (Note 1.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage (Referenced

to V

EE

, VSS ≥ VEE)

–0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient) (Referen–
ced to V

SS

for Control Inputs

and V

EE

for Switch I/O)

–0.5 to VDD + 0.5 V

I

in

Input Current (DC or Transient)

per Control Pin

±10 mA

I

SW

Switch Through Current ±25 mA

P

D

Power Dissipation,

per Package (Note 2.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

, VEE or VDD). Unused outputs must be left open.

http://onsemi.com

XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC140XXBCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

140XXB

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC140XXB

AWLYWW

TSSOP–16
DT SUFFIX

CASE 948F

14

0XXB

ALYW

1

16

See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

MC14051B, MC14052B, MC14053B

http://onsemi.com

2

MC14051B

8–Channel Analog

Multiplexer/Demultiplexer

MC14052B

Dual 4–Channel Analog

Multiplexer/Demultiplexer

MC14053B

Triple 2–Channel Analog

Multiplexer/Demultiplexer

VDD = PIN 16

V

SS

= PIN 8

V

EE

= PIN 7

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7

X

4

2

5

1

12

15

14

13

9

10

11

6

CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

3

4

2

5

1

11

15

14

12

9

10

6

CONTROLS

SWITCHES

IN/OUT

13

3

COMMONS

OUT/IN

X

Y

V

DD

= PIN 16

V

SS

= PIN 8

V

EE

= PIN 7

3

5

1

2

13

12

9

10

11

6

CONTROLS

SWITCHES

IN/OUT

14

15

4

X

Y

Z

COMMONS

OUT/IN

V

DD

= PIN 16

V

SS

= PIN 8

V

EE

= PIN 7

INHIBIT
A
B

X0
X1
X2
X3
Y0
Y1
Y2
Y3

INHIBIT
A
B

C
X0

Y0
Y1
Z0
Z1

X1

PIN ASSIGMENT

MC14051B MC14052B MC14053B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X3

X0

X1

X2

V

DD

C

B

A

X7

X

X6

X4

V

SS

V

EE

INH

X5

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X0

X

X1

X2

V

DD

B

A

X3

Y3

Y

Y2

Y0

V

SS

V

EE

INH

Y1

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X0

X1

X

Y

V

DD

C

B

A

Z

Z1

Y0

Y1

V

SS

V

EE

INH

Z0

MC14051B, MC14052B, MC14053B

http://onsemi.com

3

ELECTRICAL CHARACTERISTICS

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Test Conditions

Min

Max

Min

Typ

(3.)

Max

Min

Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

V

DD

—

VDD – 3.0 ≥ V

SS

≥ V

EE

3.0

18

3.0

—

18

3.0

18

V

ОООООО

Î

ОООООО

Î

ОООООО

Î

Quiescent Current Per

Package

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

DD

5.0
10
15

ООООО

Î

ООООО

Î

ООООО

Î

Control Inputs:

V

in

= VSS or VDD,

Switch I/O: V

EE

v V

I/O

v

VDD, and ∆V

switch

v

500 mV

(4.)

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

5.0
10
20

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

0.005

0.010

0.015

Î

Î

Î

Î

Î

Î

5.0
10
20

Î

Î

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Î

Î

150
300
600

µA

ОООООО

Î

ОООООО

Î

Total Supply Current

(Dynamic Plus
Quiescent, Per Package

ÎÎ

Î

ÎÎ

Î

I

D(AV)

5.0
10
15

ООООО

Î

ООООО

Î

TA = 25_C only (The

channel component,
(V

in

– V

out

)/Ron, is

not included.)

ООООООООООООО

Î

ООООООООООООО

Î

(0.07 µA/kHz) f + I

DD

Typical (0.20 µA/kHz) f + I

DD

(0.36 µA/kHz) f + I

DD

µA

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

ОООООО

Î

Low–Level Input Voltage

ÎÎ

Î

V

IL

5.0
10
15

ООООО

Î

Ron = per spec,
I

off

= per spec

Î

Î

—
—
—

Î

Î

1.5

3.0

4.0

—
—
—

ÎÎ

Î

2.25

4.50

6.75

Î

Î

1.5

3.0

4.0

Î

Î

—
—
—

Î

Î

1.5

3.0

4.0

V

ОООООО

Î

ОООООО

Î

High–Level Input Voltage

ÎÎ

Î

ÎÎ

Î

V

IH

5.0
10
15

ООООО

Î

ООООО

Î

Ron = per spec,
I

off

= per spec

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

3.5

7.0
11

ÎÎ

Î

ÎÎ

Î

2.75

5.50

8.25

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

V

Input Leakage Current

I

in

15

Vin = 0 or V

DD

—

± 0.1

—

±0.00001

± 0.1

—

1.0

µA

Input Capacitance

C

in

—

—

—

—

5.0

7.5

—

—

pF

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

ОООООО

Î

ОООООО

Î

Recommended

Peak–to–Peak Voltage
Into or Out of the Switch

ÎÎ

Î

ÎÎ

Î

V

I/O

—

ООООО

Î

ООООО

Î

Channel On or Off

Î

Î

Î

Î

0

Î

Î

Î

Î

V

DD

0

ÎÎ

Î

ÎÎ

Î

—

Î

Î

Î

Î

V

DD

Î

Î

Î

Î

0

Î

Î

Î

Î

V

DDVPP

ОООООО

Î

Recommended Static or

Dynamic Voltage Across
the Switch

(4.)

(Figure 5)

ÎÎ

Î

∆V

switch

—

ООООО

Î

Channel On

Î

Î

0

Î

Î

600

0

ÎÎ

Î

—

Î

Î

600

Î

Î

0

Î

Î

300

mV

Output Offset Voltage

V

OO

—

Vin = 0 V, No Load

—

—

—

10

—

—

—

µV

ОООООО

Î

ОООООО

Î

ON Resistance

ÎÎ

Î

ÎÎ

Î

R

on

5.0
10
15

ООООО

Î

ООООО

Î

∆V

switch

v 500 mV

(4.)

Vin = VIL or V

IH

(Control), and Vin =
0 to V

DD

(Switch)

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

800
400
220

—
—
—

ÎÎ

Î

ÎÎ

Î

250
120

80

Î

Î

Î

Î

1050

500
280

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1200

520
300

Ω

ОООООО

Î

∆ON Resistance Between

Any Two Channels in the
Same Package

ÎÎ

Î

∆R

on

5.0
10
15

ОООООÎÎ

Î

—
—
—

Î

Î

70
50
45

—
—
—

ÎÎ

Î

25
10
10

Î

Î

70
50
45

Î

Î

—
—
—

Î

Î

135

95
65

Ω

ОООООО

Î

ОООООО

Î

Off–Channel Leakage

Current (Figure 10)

ÎÎ

Î

ÎÎ

Î

I

off

15

ООООО

Î

ООООО

Î

Vin = VIL or V

IH

(Control) Channel to
Channel or Any One
Channel

Î

Î

Î

Î

—

Î

Î

Î

Î

± 100

—

ÎÎ

Î

ÎÎ

Î

± 0.05

Î

Î

Î

Î

± 100

Î

Î

Î

Î

—

Î

Î

Î

Î

±1000

nA

Capacitance, Switch I/O

C

I/O

—

Inhibit = V

DD

—

—

—

10

—

—

—

pF

ОООООО

Î

ОООООО

Î

Capacitance, Common O/I

ÎÎ

Î

ÎÎ

Î

C

O/I

—

ООООО

Î

ООООО

Î

Inhibit = V

DD

(MC14051B)
(MC14052B)
(MC14053B)

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

—
—
—

—
—
—

ÎÎ

Î

ÎÎ

Î

60
32
17

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

—
—
—

pF

ОООООО

Î

Capacitance, Feedthrough

(Channel Off)

ÎÎ

Î

C

I/O

—
—

ООООО

Î

Pins Not Adjacent
Pins Adjacent

Î

Î

—
—

Î

Î

———

—

ÎÎ

Î

0.15

0.47

Î

Î

—
—

Î

Î

—
—

Î

Î

——pF

3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

4. For voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the

current out of the switch may contain both V

DD

and switch input components. The reliability of the device will be unaffected unless the

Maximum Ratings are exceeded. (See first page of this data sheet.)

MC14051B, MC14052B, MC14053B

http://onsemi.com

4

ELECTRICAL CHARACTERISTICS

(5.)

(C

L

= 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)

Characteristic

Symbol

VDD – V

EE

Vdc

Typ

(6.)

All Types

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Times (Figure 6)

Switch Input to Switch Output (R

L

= 10 kΩ)

MC14051

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 26.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 11 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 9.0 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

, t

PHL

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

35
15
12

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

90
40
30

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

MC14052

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 21.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 8.0 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 7.0 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

ÎÎÎ

Î

30
12
10

ÎÎÎ

Î

ÎÎÎ

Î

75
30
25

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

MC14053

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 16.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 4.0 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 3.0 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

ÎÎÎ

Î

25

8.0

6.0

ÎÎÎ

Î

ÎÎÎ

Î

65
20
15

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Inhibit to Output (RL = 10 kΩ, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level

MC14051B

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PHZ

, t

PLZ

,

t

PZH

, t

PZL

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

350
170
140

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

700
340
280

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

MC14052B

ÎÎÎÎÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

300
155
125

ÎÎÎ

Î

600
310
250

Î

Î

ns

ООООООООООООО

Î

MC14053B

ÎÎÎÎÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

275
140
110

ÎÎÎ

Î

550
280
220

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Control Input to Output (RL = 10 kΩ, VEE = VSS)

MC14051B

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

, t

PHL

ÎÎÎ

Î

ÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

ÎÎÎ

Î

360
160
120

ÎÎÎ

Î

ÎÎÎ

Î

720
320
240

Î

Î

Î

Î

ns

ООООООООООООО

Î

MC14052B

ÎÎÎÎÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

325
130

90

ÎÎÎ

Î

650
260
180

Î

Î

ns

ООООООООООООО

Î

MC14053B

ÎÎÎÎÎÎÎ

Î

5.0
10
15

ÎÎÎ

Î

300
120

80

ÎÎÎ

Î

600
240
160

Î

Î

ns

ООООООООООООО

Î

Second Harmonic Distortion

(R

L

= 10KΩ, f = 1 kHz) Vin = 5 V

PP

ÎÎÎ

Î

—

ÎÎÎ

Î

10

ÎÎÎ

Î

0.07

ÎÎÎ

Î

—

Î

Î

%

ООООООООООООО

Î

Bandwidth (Figure 7)

(R

L

= 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF

20 Log (V

out/Vin

) = – 3 dB)

ÎÎÎ

Î

BW

ÎÎÎ

Î

10

ÎÎÎ

Î

17

ÎÎÎ

Î

—

Î

Î

MHz

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Off Channel Feedthrough Attenuation (Figure 7)

R

L

= 1KΩ, Vin = 1/2 (VDD – VEE) p–p

f

in

= 4.5 MHz — MC14051B

f

in

= 30 MHz — MC14052B

f

in

= 55 MHz — MC14053B

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

—

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

10

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

– 50

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

—

Î

Î

Î

Î

Î

Î

dB

ООООООООООООО

Î

Channel Separation (Figure 8)

(R

L

= 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,

f

in

= 3.0 MHz

ÎÎÎ

Î

—

ÎÎÎ

Î

10

ÎÎÎ

Î

– 50

ÎÎÎ

Î

—

Î

Î

dB

ООООООООООООО

Î

Crosstalk, Control Input to Common O/I (Figure 9)

(R

1

= 1 kΩ, RL = 10 kΩ

Control t

TLH

= t

THL

= 20 ns, Inhibit = VSS)

ÎÎÎ

Î

—

ÎÎÎ

Î

10

ÎÎÎ

Î

75

ÎÎÎ

Î

—

Î

Î

mV

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

MC14051B, MC14052B, MC14053B

http://onsemi.com

5

Figure 1. Switch Circuit Schematic

IN/OUT

LEVEL
CONVERTED
CONTROL

V

DD

V

EE

V

DD

V

DD

V

DD

OUT/IN

V

EE

IN/OUT OUT/IN

CONTROL

TRUTH TABLE

Control Inputs

Select

ON Switches

Inhibit

C* B A MC14051B MC14052B MC14053B

0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 01 X1 Y1 X1 Z0 Y0 X1
0 0 10 X2 Y2 X2 Z0 Y1 X0
0 0 11 X3 Y3 X3 Z0 Y1 X1

0 1 0 0 X4 Z1 Y0 X0
0 1 01 X5 Z1 Y0 X1
0 1 10 X6 Z1 Y1 X0
0 1 11 X7 Z1 Y1 X1

1 x x x None None None

*Not applicable for MC14052
x = Don’t Care

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

16 V

DD

8VSS7V

EE

13 X

3Y

BINARY TO 1–OF–4

DECODER WITH

INHIBIT

LEVEL

CONVERTER

INH 6

A10
B9

X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4

BINARY TO 1–OF–2

DECODER WITH

INHIBIT

LEVEL

CONVERTER

16 V

DD

8VSS7V

EE

14 X

15 Y

4Z

INH 6

A11
B10
C9

X0 12
X1 13
Y0 2
Y1 1
Z0 5
Z1 3

Figure 2. MC14051B Functional Diagram

INH 6

A11
B10
C9

X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4

8VSS7V

EE

16 V

DD

3X

BINARY TO 1–OF–8

DECODER WITH

INHIBIT

LEVEL

CONVERTER

MC14051B, MC14052B, MC14053B

http://onsemi.com

6

TEST CIRCUITS

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output

Figure 7. Bandwidth and Off–Channel

Feedthrough Attenuation

Figure 8. Channel Separation

(Adjacent Channels Used For Setup)

Figure 9. Crosstalk, Control Input to

Common O/I

Figure 10. Off Channel Leakage

CONTROL

SECTION

OF IC

SOURCE

V

ON SWITCH

PULSE

GENERATOR

INH

A
B
C

R

L

C

L

V

out

VDDVEEVEEV

DD

INH

A
B
C

V

SS

V

in

R

L

CL = 50 pF

V

out

VDD – V

EE

2

INH

A
B
C

OFF

ON

R

L

R

L

CL = 50 pF

V

out

V

in

VDD – V

EE

2

INH

A
B
C

R1

R

L

CL = 50 pF

V

out

CONTROL

SECTION

OF IC

OFF CHANNEL UNDER TEST

OTHER
CHANNEL(S)

COMMON

V

DD

V

EE

V

EE

V

DD

V

EE

V

DD

NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.

A, B, and C inputs used to turn ON
or OFF
the switch under test.

LOAD

MC14051B, MC14052B, MC14053B

http://onsemi.com

7

Figure 11. Channel Resistance (RON) Test Circuit

V

DD

VEE = V

SS

10 k

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

1 kΩ

RANGE

X–Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

Figure 12. V

DD

= 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

Figure 14. VDD = 2.5 V, VEE = – 2.5 V

R

ON

, “ON” RESISTANCE (OHMS)

700
600

500

400

300

200

0

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C
–55°C

Figure 15. Comparison at 25°C, VDD = –V

EE

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

V

in

, INPUT VOLTAGE (VOLTS)

TA = 25°C

VDD = 2.5 V

5.0 V

7.5 V

MC14051B, MC14052B, MC14053B

http://onsemi.com

8

APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter
detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control
signal is used to directly control a 9 V

p–p

analog signal.

The digital control logic levels are determined by V

DD

and VSS. The VDD voltage is the logic high voltage; the V

SS

voltage is logic low . For the example, VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage
determines the maximum swing below V

SS

. For the
example, VDD – VSS = 5 V maximum swing above VSS;
VSS – VEE = 5 V maximum swing below VSS. The example
shows a ± 4.5 V signal which allows a 1/2 volt margin at each

peak. If voltage transients above V

DD

and/or below VEE are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.

The absolute maximum potential difference between

V

DD

and VEE is 18.0 V . Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VEE.

Balanced supplies are not required. However, VSS must

be greater than or equal to V

EE

. For example, VDD = + 10
V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table
below.

Figure A. Application Example

+5 V –5 V

V

DD

V

SS

V

EE

9 V

p–p

ANALOG SIGNAL

0–TO–5 V DIGITAL

CONTROL SIGNALS

SWITCH

I/O

INHIBIT ,

A, B, C

COMMON

O/I

9 V

p–p

ANALOG SIGNAL

+4.5 V

–4.5 V

GND

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

MC14051B
MC14052B
MC14053B

Figure B. External Germanium or Schottky Clipping Diodes

V

DD

V

DD

V

EE

V

EE

D

X

D

X

D

X

D

X

ANALOG

I/O

COMMON

O/I

POSSIBLE SUPPLY CONNECTIONS

ÎÎ

Î

ÎÎ

Î

V

DD

In Volts

ÎÎÎ

Î

ÎÎÎ

Î

V

SS

In Volts

ÎÎ

Î

ÎÎ

Î

V

EE

In Volts

ООООО

Î

ООООО

Î

Control Inputs

Logic High/Logic Low

In Volts

ООООООО

Î

ООООООО

Î

Maximum Analog Signal Range

In Volts

+ 8

0

– 8

+ 8/0

+ 8 to – 8 = 16 V

p–p

+ 5

0

– 12

+ 5/0

+ 5 to – 12 = 17 V

p–p

+ 5

0

0

+ 5/0

+ 5 to 0 = 5 V

p–p

+ 5

0

– 5

+ 5/0

+ 5 to – 5 = 10 V

p–p

+ 10

+ 5

– 5

+ 10/ + 5

+ 10 to – 5 = 15 V

p–p

MC14051B, MC14052B, MC14053B

http://onsemi.com

9

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53

F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74
M 0 10 0 10

S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14051B, MC14052B, MC14053B

http://onsemi.com

10

P ACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC14051B, MC14052B, MC14053B

http://onsemi.com

11

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14051B, MC14052B, MC14053B

http://onsemi.com

12

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14051BCP PDIP–16 2000 Units per Box
MC14051BD SOIC–16 48 Units per Rail
MC14051BDR2 SOIC–16 2500 Units / Tape & Reel
MC14051BDT TSSOP–16 96 Units per Rail
MC14051BDTEL TSSOP–16 2000 Units / Tape & Reel
MC14051BDTR2 TSSOP–16 2500 Units / T ape & Reel
MC14051BF SOEIAJ–16 See Note 7.
MC14051BFEL SOEIAJ–16 See Note 7.

MC14052BCP PDIP–16 2000 Units per Box
MC14052BD SOIC–16 48 Units per Rail
MC14052BDR2 SOIC–16 2500 Units / Tape & Reel
MC14052BDT TSSOP–16 96 Units per Rail
MC14052BDTR2 TSSOP–16 2500 Units / T ape & Reel
MC14052BF SOEIAJ–16 See Note 7.
MC14052BFEL SOEIAJ–16 See Note 7.

ORDERING & SHIPPING INFORMATION:

MC14053BCP PDIP–16 2000 Units per Box
MC14053BD SOIC–16 48 Units per Rail
MC14053BDR2 SOIC–16 2500 Units / Tape & Reel
MC14053BDT TSSOP–16 96 Units per Rail
MC14053BDTEL TSSOP–16 2000 Units / Tape & Reel
MC14053BDTR2 TSSOP–16 2500 Units / T ape & Reel
MC14053BF SOEIAJ–16 See Note 7.
MC14053BFEL SOEIAJ–16 See Note 7.

7. For ordering information on the EIAJ version of the SOIC
packages, please contact your local ON Semiconductor rep­resentative.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support

Phone: [phone] (T ue–Fri 9:00am to 1:00pm, Hong Kong T ime)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC14051B/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–[e-mail]

French Phone: [phone] (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[e-mail]

English Phone: [phone] (M–F 12:00pm to 5:00pm UK Time)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy , England, Ireland