Datasheet MC14051BCL, MC14053BCL, MC14051BCP, MC14051BD, MC14052BCL Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

1

MC14051B MC14052B MC14053B

Analog
Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitally–controlled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage
range can be achieved.

• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be v V

SS

• Linearized Transfer Characteristics

• Low–noise – 12 nV/√Cycle

, f ≥ 1.0 kHz Typical

• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

• For 4PDT Switch, See MC14551B

• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage (Referenced to VEE,
VSS ≥ VEE)

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Inputs and
VEE for Switch I/O)

– 0.5 to VDD + 0.5

V

I

in

Input Current (DC or Transient),
per Control Pin

± 10

mA

I

sw

Switch Through Current

± 25

mA

P

D

Power Dissipation. per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:“P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14051B

8–Channel Analog

Multiplexer/Demultiplexer

MC14052B

Dual 4–Channel Analog

Multiplexer/Demultiplexer

MC14053B

Triple 2–Channel Analog

Multiplexer/Demultiplexer

VDD = PIN 16

VSS = PIN 8
VEE = PIN 7

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7

X

4

2

5

1

12

15

14

13

9

10

11

6

CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

3

4

2

5

1

11

15

14

12

9

10

6

CONTROLS

SWITCHES

IN/OUT

13

3

COMMONS

OUT/IN

X

Y

VDD = PIN 16

VSS = PIN 8
VEE = PIN 7

3

5

1

2

13

12

9

10

11

6

CONTROLS

SWITCHES

IN/OUT

14

15

4

X

Y

Z

COMMONS

OUT/IN

VDD = PIN 16

VSS = PIN 8
VEE = PIN 7

INHIBIT
A
B

X0
X1
X2
X3
Y0

Y1
Y2
Y3

INHIBIT
A
B

C
X0

Y0
Y1
Z0
Z1

X1

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94

MC14051B
MC14052B
MC14053B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

2

ELECTRICAL CHARACTERISTICS

– 55_C

25_C

125_C

Characteristic

Symbol

VDDTest Conditions

Min

Max

Min

Typ #

Max

Min

Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

V

DD

—

VDD – 3.0 ≥ VSS ≥ V

EE

3.0

18

3.0

—

18

3.0

18

V

Quiescent Current Per

Package

I

DD

5.0
10
15

Control Inputs:

Vin = VSS or VDD,

Switch I/O: VEE v V

I/O

v

VDD, and

∆V

switch

v 500 mV**

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µA

Total Supply Current

(Dynamic Plus
Quiescent, Per Package

I

D(AV)

5.0
10
15

TA = 25_C only (The

channel component,
(Vin – V

out

)/Ron, is

not included.)

(0.07 µA/kHz) f + I

DD

Typical (0.20 µA/kHz) f + I

DD

(0.36 µA/kHz) f + I

DD

µA

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

Low–Level Input Voltage

V

IL

5.0
10
15

Ron = per spec,
I

off

= per spec

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

V

High–Level Input Voltage

V

IH

5.0
10
15

Ron = per spec,
I

off

= per spec

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

V

Input Leakage Current

I

in

15

Vin = 0 or V

DD

—

± 0.1

—

±0.00001

± 0.1

—

1.0

µA

Input Capacitance

C

in

—

—

—

—

5.0

7.5

—

—

pF

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

Recommended

Peak–to–Peak Voltage
Into or Out of the Switch

V

I/O

—

Channel On or Off

0

V

DD

0

—

V

DD

0

V

DDVPP

Recommended Static or

Dynamic Voltage Across
the Switch** (Figure 5)

∆V

switch

—

Channel On

0

600

0

—

600

0

300

mV

Output Offset Voltage

V

OO

—

Vin = 0 V, No Load

—

—

—

10

—

—

—

µV

ON Resistance

R

on

5.0
10
15

∆V

switch

v 500 mV**,

Vin = VIL or V

IH

(Control), and Vin =
0 to VDD (Switch)

—
—
—

800
400
220

—
—
—

250
120

80

1050

500
280

—
—
—

1200

520
300

Ω

∆ON Resistance Between

Any Two Channels in the
Same Package

∆R

on

5.0
10
15

—
—
—

70
50
45

—
—
—

25
10
10

70
50
45

—
—
—

135

95
65

Ω

Off–Channel Leakage

Current (Figure 10)

I

off

15

Vin = VIL or V

IH

(Control) Channel to
Channel or Any One
Channel

—

± 100

—

± 0.05

± 100

—

±1000

nA

Capacitance, Switch I/O

C

I/O

—

Inhibit = V

DD

—

—

—

10

—

—

—

pF

Capacitance, Common O/I

C

O/I

—

Inhibit = V

DD

(MC14051B)
(MC14052B)
(MC14053B)

—
—
—

—
—
—

—
—
—

60
32
17

—
—
—

—
—
—

—
—
—

pF

Capacitance, Feedthrough

(Channel Off)

C

I/O

——Pins Not Adjacent

Pins Adjacent

———

—

—
—

0.15

0.47

—
—

————pF

#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
*For voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA

3

MC14051B MC14052B MC14053B

ELECTRICAL CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)

Characteristic

Symbol

VDD – V

EE

Vdc

Typ #

All Types

Max

Unit

Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 kΩ)

MC14051

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 26.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 11 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 9.0 ns

t

PLH

, t

PHL

5.0
10
15

35
15
12

90
40
30

ns

MC14052

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 21.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 8.0 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 7.0 ns

5.0
10
15

30
12
10

75
30
25

ns

MC14053

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 16.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 4.0 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 3.0 ns

5.0
10
15

25

8.0

6.0

65
20
15

ns

Inhibit to Output (RL = 10 kΩ, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level

MC14051B

t

PHZ

, t

PLZ

,

t

PZH

, t

PZL

5.0
10
15

350
170
140

700
340
280

ns

MC14052B

5.0
10
15

300
155
125

600
310
250

ns

MC14053B

5.0
10
15

275
140
110

550
280
220

ns

Control Input to Output (RL = 10 kΩ, VEE = VSS)

MC14051B

t

PLH

, t

PHL

5.0
10
15

360
160
120

720
320
240

ns

MC14052B

5.0
10
15

325
130

90

650
260
180

ns

MC14053B

5.0
10
15

300
120

80

600
240
160

ns

Second Harmonic Distortion

(RL = 10KΩ, f = 1 kHz) Vin = 5 V

PP

—

10

0.07

—

%

Bandwidth (Figure 7)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
20 Log (V

out/Vin

) = – 3 dB)

BW

10

17

—

MHz

Off Channel Feedthrough Attenuation (Figure 7)

RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B

—

10

– 50

—

dB

Channel Separation (Figure 8)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,
fin = 3.0 MHz

—

10

– 50

—

dB

Crosstalk, Control Input to Common O/I (Figure 9)

(R1 = 1 kΩ, RL = 10 kΩ
Control t

TLH

= t

THL

= 20 ns, Inhibit = VSS)

—

10

75

—

mV

*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs
must be left open.

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

4

Figure 1. Switch Circuit Schematic

IN/OUT

LEVEL
CONVERTED
CONTROL

V

DD

V

EE

V

DD

V

DD

V

DD

OUT/IN

V

EE

IN/OUT OUT/IN

CONTROL

TRUTH TABLE

Control Inputs

Select

ON Switches

Inhibit

C* B A MC14051B MC14052B MC14053B

0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1
0 0 1 0 X2 Y2 X2 Z0 Y1 X0
0 0 1 1 X3 Y3 X3 Z0 Y1 X1

0 1 0 0 X4 Z1 Y0 X0
0 1 0 1 X5 Z1 Y0 X1
0 1 1 0 X6 Z1 Y1 X0
0 1 1 1 X7 Z1 Y1 X1

1 x x x None None None

*Not applicable for MC14052
x = Don’t Care

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

16 V

DD

8 VSS7 V

EE

13 X

3 Y

BINARY TO 1–OF–4

DECODER WITH

INHIBIT

LEVEL

CONVERTER

INH 6

A 10
B 9

X0 12
X1 14
X2 15

X3 11

Y0 1
Y1 5
Y2 2
Y3 4

BINARY TO 1–OF–2

DECODER WITH

INHIBIT

LEVEL

CONVERTER

16 V

DD

8 VSS7 V

EE

14 X

15 Y

4 Z

INH 6

A 11
B 10
C 9

X0 12
X1 13
Y0 2
Y1 1

Z0 5
Z1 3

Figure 2. MC14051B Functional Diagram

INH 6

A 11
B 10

C 9

X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4

8 VSS7 V

EE

16 V

DD

3 X

BINARY TO 1–OF–8

DECODER WITH

INHIBIT

LEVEL

CONVERTER

MOTOROLA CMOS LOGIC DATA

5

MC14051B MC14052B MC14053B

TEST CIRCUITS

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output

Figure 7. Bandwidth and Off–Channel

Feedthrough Attenuation

Figure 8. Channel Separation

(Adjacent Channels Used For Setup)

Figure 9. Crosstalk, Control Input to

Common O/I

Figure 10. Off Channel Leakage

CONTROL

SECTION

OF IC

SOURCE

V

ON SWITCH

PULSE

GENERATOR

INH

A
B
C

R

L

C

L

V

out

VDDVEEVEEV

DD

INH

A
B
C

V

SS

V

in

R

L

CL = 50 pF

V

out

VDD – V

EE

2

INH

A
B
C

OFF

ON

R

L

R

L

CL = 50 pF

V

out

V

in

VDD – V

EE

2

INH

A
B
C

R1

R

L

CL = 50 pF

V

out

CONTROL

SECTION

OF IC

OFF CHANNEL UNDER TEST

OTHER
CHANNEL(S)

COMMON

V

DD

V

EE

V

EE

V

DD

V

EE

V

DD

NOTE: See also Figures 7 and 8 on Page 6–51.

A, B, and C inputs used to turn ON or OFF
the switch under test.

LOAD

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

6

Figure 11. Channel Resistance (RON) Test Circuit

V

DD

VEE = V

SS

10 k

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

1 k

Ω

RANGE

X–Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

Figure 14. VDD = 2.5 V, VEE = – 2.5 V

R

ON

, “ON” RESISTANCE (OHMS)

700
600

500

400

300

200

0

100

–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

–55°C

Figure 15. Comparison at 25°C, VDD = –V

EE

R

ON

, “ON” RESISTANCE (OHMS)

350
300

250

200

150

100

0

50

–8.0–10 –6.0 – 4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 25°C

VDD = 2.5 V

5.0 V

7.5 V

PIN ASSIGMENT

MC14051B MC14052B MC14053B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X3

X0

X1

X2

V

DD

C

B

A

X7

X

X6

X4

V

SS

V

EE

INH

X5

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X0

X

X1

X2

V

DD

B

A

X3

Y3

Y

Y2

Y0

V

SS

V

EE

INH

Y1

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X0

X1

X

Y

V

DD

C

B

A

Z

Z1

Y0

Y1

V

SS

V

EE

INH

Z0

MOTOROLA CMOS LOGIC DATA

7

MC14051B MC14052B MC14053B

APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter de­tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig­nal is used to directly control a 9 V

p–p

analog signal.

The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS volt­age is logic low. For the example, VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VEE. The VDD voltage determines the maximum recom­mended peak above VSS. The VEE voltage determines the
maximum swing below VSS. For the example, VDD – VSS =
5 V maximum swing above VSS; VSS – VEE = 5 V maximum
swing below VSS. The example shows a ± 4.5 V signal which
allows a 1/2 volt margin at each peak. If voltage transients

above VDD and/or below VEE are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.

The

absolute

maximum potential difference between V

DD

and VEE is 18.0 V . Most parameters are specified up to 15 V
which is t he

recommended

maximum d ifference between

VDD and VEE.

Balanced supplies are not required. However, VSS must
be greater than or equal to VEE. For example, VDD = + 10 V ,
VSS = + 5 V, and VEE – 3 V is acceptable. See the Table
below.

Figure A. Application Example

+5 V –5 V

V

DD

V

SS

V

EE

9 V

p–p

ANALOG SIGNAL

0–TO–5 V DIGITAL

CONTROL SIGNALS

SWITCH

I/O

INHIBIT,

A, B, C

COMMON

O/I

9 V

p–p

ANALOG SIGNAL

+

4.5 V

–

4.5 V

GND

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

MC14051B
MC14052B
MC14053B

Figure B. External Germanium or Schottky Clipping Diodes

V

DD

V

DD

V

EE

V

EE

D

X

D

X

D

X

D

X

ANALOG

I/O

COMMON

O/I

POSSIBLE SUPPLY CONNECTIONS

V

DD

In Volts

V

SS

In Volts

V

EE

In Volts

Control Inputs

Logic High/Logic Low

In Volts

Maximum Analog Signal Range

In Volts

+ 8

0

– 8

+ 8/0

+ 8 to – 8 = 16 V

p–p

+ 5

0

– 12

+ 5/0

+ 5 to – 12 = 17 V

p–p

+ 5

0

0

+ 5/0

+ 5 to 0 = 5 V

p–p

+ 5

0

– 5

+ 5/0

+ 5 to – 5 = 10 V

p–p

+ 10

+ 5

– 5

+ 10/ + 5

+ 10 to – 5 = 15 V

p–p

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

8

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC

F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31

L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

9

MC14051B MC14052B MC14053B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

_ _ _ _

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MC14051B/D

*MC14051B/D*

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