Datasheet MC14050BFEL, MC14050BFL1, MC14050BFL2, MC14050BFR1, MC14050BFR2 Datasheet (MOTOROLA)
...Page 1
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14049B/D
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P–Channel and N–Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, V
DD
.
The input–signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. T wo TTL/DTL loads can be driven
when the devices are used as a CMOS–to–TTL/DTL converter (V
DD
= 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
• High Source and Sink Currents
• High–to–Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• V
IN
can exceed V
DD
• Meets JEDEC B Specifications
• Improved ESD Protection On All Inputs
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
Input Voltage Range
(DC or Transient)
–0.5 to +18.0 V
V
out
Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5 V
I
in
Input Current
(DC or Transient) per Pin
±10 mA
I
out
Output Current
(DC or Transient) per Pin
±45 mA
P
D
Power Dissipation,
per Package (Note 3.)
(Plastic)
(SOIC)
825
740
mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the V
SS
pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high–impedance circuit. For proper operation, the
ranges V
SS
≤ Vin ≤ 18 V and VSS ≤ V
out
≤ V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or VDD). Unused outputs must be left open.
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XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14049BCP PDIP–16 2000/Box
MC14049BD SOIC–16 2400/Box
MC14049BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
140XXB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC140XXB
AWLYWW
MC14049BF SOEIAJ–16 See Note 1.
MC14050BCP PDIP–16 2000/Box
MC14050BD SOIC–16 2400/Box
MC14050BDR2 SOIC–16 2500/Tape & Reel
MC14050BDTEL TSSOP–16 2000/Tape & Reel
MC14050BF SOEIAJ–16 See Note 1.
MC14050BFEL SOEIAJ–16 See Note 1.
TSSOP–16
DT SUFFIX
CASE 948F
14
0XXB
ALYW
1
16
Page 2
MC14049B, MC14050B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
OUT
E
NC
IN
F
OUT
F
NC
IN
D
OUT
D
IN
E
OUT
B
IN
A
OUT
A
V
DD
V
SS
IN
C
OUT
C
IN
B
LOGIC DIAGRAM
MC14049B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
V
SS
= PIN 8
V
DD
= PIN 1
MC14050B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
V
SS
= PIN 8
V
DD
= PIN 1
Page 3
MC14049B, MC14050B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
+ 25_C
+ 125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
ОООООООО
Î
Output Voltage “0” Level
V
in
= V
DD
ÎÎ
Î
V
OL
Î
Î
5.0
10
15
Î
Î
—
—
—
Î
Î
0.05
0.05
0.05
ÎÎ
Î
—
—
—
Î
Î
0
0
0
ÎÎ
Î
0.05
0.05
0.05
Î
Î
—
—
—
Î
Î
0.05
0.05
0.05
Î
Î
Vdc
ОООООООО
Î
“1” Level
V
in
= 0
ÎÎ
Î
V
OH
Î
Î
5.0
10
15
Î
Î
4.95
9.95
14.95
Î
Î
—
—
—
ÎÎ
Î
4.95
9.95
14.95
Î
Î
5.0
10
15
ÎÎ
Î
—
—
—
Î
Î
4.95
9.95
14.95
Î
Î
—
—
—
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
Input Voltage “0” Level
(V
O
= 4.5 Vdc)
(V
O
= 9.0 Vdc)
(V
O
= 13.5 Vdc)
ÎÎ
Î
ÎÎ
Î
V
IL
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
1.5
3.0
4.0
ÎÎ
Î
ÎÎ
Î
—
—
—
Î
Î
Î
Î
2.25
4.50
6.75
ÎÎ
Î
ÎÎ
Î
1.5
3.0
4.0
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
1.5
3.0
4.0
Î
Î
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
“1” Level
(V
O
= 0.5 Vdc)
(V
O
= 1.0 Vdc)
(V
O
= 1.5 Vdc)
ÎÎ
Î
ÎÎ
Î
V
IH
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
3.5
7.0
11
Î
Î
Î
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
3.5
7.0
11
Î
Î
Î
Î
2.75
5.50
8.25
ÎÎ
Î
ÎÎ
Î
—
—
—
Î
Î
Î
Î
3.5
7.0
11
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
ÎÎ
Î
ÎÎ
Î
I
OH
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
– 1.6
– 1.6
– 4.7
Î
Î
Î
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
– 1.25
– 1.30
– 3.75
Î
Î
Î
Î
– 2.5
– 2.6
– 10
ÎÎ
Î
ÎÎ
Î
—
—
—
Î
Î
Î
Î
– 1.0
– 1.0
– 3.0
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
mAdc
ОООООООО
Î
ОООООООО
Î
(VOL = 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
ÎÎ
Î
ÎÎ
Î
I
OL
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
3.75
10
30
Î
Î
Î
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
3.2
8.0
24
Î
Î
Î
Î
6.0
16
40
ÎÎ
Î
ÎÎ
Î
—
—
Î
Î
Î
Î
2.6
6.6
19
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance (Vin = 0)
C
in
—
—
—
—
10
20
—
—
pF
ОООООООО
Î
Quiescent Current (Per Package)
ÎÎ
Î
I
DD
Î
Î
5.0
10
15
Î
Î
—
—
—
Î
Î
1.0
2.0
4.0
ÎÎ
Î
—
—
—
Î
Î
0.002
0.004
0.006
ÎÎ
Î
1.0
2.0
4.0
Î
Î
—
—
—
Î
Î
30
60
120
Î
Î
µAdc
ОООООООО
Î
ОООООООО
Î
ОООООООО
Î
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
per package)
(C
L
= 50 pF on all outputs, all
buffers switching
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
I
T
Î
Î
Î
Î
Î
Î
5.0
10
15
ООООООООООООООО
Î
ООООООООООООООО
Î
ООООООООООООООО
Î
IT = (1.8 µA/kHz) f + I
DD
IT = (3.5 µA/kHz) f + I
DD
IT = (5.3 µA/kHz) f + I
DD
Î
Î
Î
Î
Î
Î
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at + 25_C
6. To calculate total supply current at loads other than 50 pF:
I
T(CL
) = IT(50 pF) + (CL – 50) Vfk
Where:
I
T
is in µA (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.
Page 4
MC14049B, MC14050B
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4
AC SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, TA = + 25_C)
ООООООООООООО
Î
Characteristic
ÎÎÎ
Î
Symbol
ÎÎ
Î
V
DD
Vdc
ÎÎ
Î
Min
ÎÎ
Î
Typ
(8.)
ÎÎ
Î
Max
Î
Î
Unit
ООООООООООООО
Î
Output Rise Time
t
TLH
= (0.7 ns/pF) CL + 65 ns
t
TLH
= (0.25 ns/pF) CL + 37.5 ns
t
TLH
= (0.2 ns/pF) CL + 30 ns
ÎÎÎ
Î
t
TLH
ÎÎ
Î
5.0
10
15
ÎÎ
Î
—
—
—
ÎÎ
Î
100
50
40
ÎÎ
Î
160
80
60
Î
Î
ns
ООООООООООООО
Î
ООООООООООООО
Î
Output Fall Time
t
THL
= (0.2 ns/pF) CL + 30 ns
t
THL
= (0.06 ns/pF) CL + 17 ns
t
THL
= (0.04 ns/pF) CL + 13 ns
ÎÎÎ
Î
ÎÎÎ
Î
t
THL
ÎÎ
Î
ÎÎ
Î
5.0
10
15
ÎÎ
Î
ÎÎ
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
40
20
15
ÎÎ
Î
ÎÎ
Î
60
40
30
Î
Î
Î
Î
ns
ООООООООООООО
Î
ООООООООООООО
Î
Propagation Delay Time
t
PLH
= (0.33 ns/pF) CL + 63.5 ns
t
PLH
= (0.19 ns/pF) CL + 30.5 ns
t
PLH
= (0.06 ns/pF) CL + 27 ns
ÎÎÎ
Î
ÎÎÎ
Î
t
PLH
ÎÎ
Î
ÎÎ
Î
5.0
10
15
ÎÎ
Î
ÎÎ
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
80
40
30
ÎÎ
Î
ÎÎ
Î
140
80
60
Î
Î
Î
Î
ns
ООООООООООООО
Î
ООООООООООООО
Î
Propagation Delay Time
t
PHL
= (0.2 ns/pF) CL + 30 ns
t
PHL
= (0.1 ns/pF) CL + 15 ns
t
PHL
= (0.05 ns/pF) CL + 12.5 ns
ÎÎÎ
Î
ÎÎÎ
Î
t
PHL
ÎÎ
Î
ÎÎ
Î
5.0
10
15
ÎÎ
Î
ÎÎ
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
40
20
15
ÎÎ
Î
ÎÎ
Î
80
40
30
Î
Î
Î
Î
ns
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Typical Output Source Characteristics Figure 2. Typical Output Sink Characteristics
MC14049B MC14050B MC14049B MC14050B
V
DD
V
SS
V
DD
V
SS
1
8
1
8
I
OL
I
OH
V
OH
V
OL
VDS = VOH – V
DD
V
DD
V
SS
1
8
I
OL
V
OL
V
DD
V
SS
1
8
I
OH
V
OH
VDD = V
OL
I
OH
,
OUT
P
UT
SOU
R
CE
CU
RR
NT
(m
A
dc)
I
OL
, OUTPUT SINK CURRENT (mAdc)
–50
–40
–30
–20
–10
0
–10 –8.0 –6.0 –4.0 –2.0 0
V
DS
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
VGS = 5.0 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 15 Vdc
160
120
80
40
0
0 2.0 4.0 6.0 8.0 10
V
DS
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
VGS = 15 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 5.0 Vdc
Page 5
MC14049B, MC14050B
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5
Figure 3. Ambient Temperature Power Derating
P
D
, MAXIMUM POWER DISSIPATION (mW)
PER PACKAGE
1200
1100
1000
900
825
800
740
700
600
500
400
300
200
100
0
175150125100755025
T
A
, AMBIENT TEMPERATURE (°C)
175 mW (P)
120 mW (D)
(P) PDIP
(D) SOIC
t
PHL
Figure 4. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
VSS8
1
C
L
V
out
V
in
#
#Invert on MC14049B only
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
90%
50%
10%
90%
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
PHL
t
THL
t
PHL
t
PLH
t
TLH
t
THL
OUTPUT
MC14049B
OUTPUT
MC14050B
INPUT
Page 6
MC14049B, MC14050B
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6
P ACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
Page 7
MC14049B, MC14050B
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7
P ACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
____
SECTION N–N
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
Page 8
MC14049B, MC14050B
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8
P ACKAGE DIMENSIONS
H
E
A
1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
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