Datasheet MC14050BD, MC14050BCL, MC14050BCP, MC14049BD, MC14049BCL Datasheet (Motorola)
...Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14049B MC14050B
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex
Buffer are constructed with MOS P–Channel and N–Channel enhancement
mode devices in a single monolithic structure. These complementary MOS
devices find primary use where low power dissipation and/or high noise
immunity is desired. These devices provide logic level conversion using only
one supply voltage, VDD.
The input–signal high level (VIH) can exceed the VDD supply voltage for
logic level conversions. Two TTL/DTL loads can be driven when the devices
are used as a CMOS–to–TTL/DTL converter (VDD = 5.0 V, VOL v 0.4 V,
IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these devices;
consequently connections to these terminals will not affect circuit operation.
• High Source and Sink Currents
• High–to–Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• VIN can exceed V
DD
• Meets JEDEC B Specifications
• Improved ESD Protection On All Inputs
MAXIMUM RATINGS1 (Voltages Referenced to V
SS
)
Characteristic
Symbol
Value
Unit
DC Supply Voltage
V
DD
– 0.5 to + 18.0
Vdc
Input Voltage (DC or Transient)
V
IN
– 0.5 to + 18.0
Vdc
Output Voltage (DC or Transient)
V
out
– 0.5 to VDD + 0.5
Vdc
Input Current (DC or Transient), per Pin
I
in
± 10
mA
Output Current (DC or Transient), per Pin
I
out
+ 45
mA
Power Dissipation, per Package
2
(Plastic/Ceramic)
(SOIC)
P
D
825
740
mW
Storage Temperature
T
stg
– 65 to + 150
_
C
Lead Temperature (8 – Second Soldering)
T
L
260
_
C
1
Maximum Ratings are those values beyond which damage to the device may occur.
2
Temperature Derating: See Figure 3.
LOGIC DIAGRAM
MC14049B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
MC14050B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
OUT
E
NC
IN
F
OUT
F
NC
IN
D
OUT
D
IN
E
OUT
B
IN
A
OUT
A
V
DD
V
SS
IN
C
OUT
C
IN
B
Page 2
MOTOROLA CMOS LOGIC DATAMC14049B MC14050B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
+ 25_C
+ 125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
1
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = V
DD
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
10
15
– 1.6
– 1.6
– 4.7
—
—
—
– 1.25
– 1.30
– 3.75
– 2.5
– 2.6
– 10
—
—
—
– 1.0
– 1.0
– 3.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
3.75
10
30
—
—
—
3.2
8.0
24
6.0
16
40
—
—
2.6
6.6
19
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance (Vin = 0)
C
in
—
—
—
—
10
20
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current (Per Package)
I
DD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
30
60
120
µAdc
Total Supply Current
2,3
(Dynamic plus Quiescent,
per package)
(CL = 50 pF on all outputs, all
buffers switching
I
T
5.0
10
15
IT = (1.8 µA/kHz) f + I
DD
IT = (3.5 µA/kHz) f + I
DD
IT = (5.3 µA/kHz) f + I
DD
µAdc
1
Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
2
The formulas given are for the typical characteristics only at + 25_C
3
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
Where:
I
T
is in µA (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields
referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high-impedance circuit. For proper operation, the ranges VSS v Vin v 18 V and VSS v V
out
v VDD are
recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be
left open.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14049B MC14050B
AC SWITCHING CHARACTERISTICS1 (C
L
= 50 pF, TA = + 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
V
DD
Vdc
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Min
Typ
2
Max
Unit
Output Rise Time
t
TLH
= (0.7 ns/pF) CL + 65 ns
t
TLH
= (0.25 ns/pF) CL + 37.5 ns
t
TLH
= (0.2 ns/pF) CL + 30 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
TLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
100
50
40
160
80
60
ns
Output Fall Time
t
THL
= (0.2 ns/pF) CL + 30 ns
t
THL
= (0.06 ns/pF) CL + 17 ns
t
THL
= (0.04 ns/pF) CL + 13 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
THL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
40
20
15
60
40
30
ns
Propagation Delay Time
t
PLH
= (0.33 ns/pF) CL + 63.5 ns
t
PLH
= (0.19 ns/pF) CL + 30.5 ns
t
PLH
= (0.06 ns/pF) CL + 27 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
80
40
30
140
80
60
ns
Propagation Delay Time
t
PHL
= (0.2 ns/pF) CL + 30 ns
t
PHL
= (0.1 ns/pF) CL + 15 ns
t
PHL
= (0.05 ns/pF) CL + 12.5 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
40
20
15
80
40
30
ns
1
The formulas given are for the typical characteristics only at 25_C.
2
Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Typical Output Source Characteristics Figure 2. Typical Output Sink Characteristics
MC14049B MC14050B MC14049B MC14050B
V
DD
V
SS
V
DD
V
SS
1
8
1
8
I
OL
I
OH
V
OH
V
OL
VDS = VOH – V
DD
V
DD
V
SS
1
8
I
OL
V
OL
V
DD
V
SS
1
8
I
OH
V
OH
VDD = V
OL
I
OH
, OUTPUT SOURCE CURRNT (mAdc)
I
OL
, OUTPUT SINK CURRENT (mAdc)
–50
–40
–30
–20
–10
0
–10 –8.0 –6.0 –4.0 –2.0 0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
VGS = 5.0 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 15 Vdc
160
120
80
40
0
0 2.0 4.0 6.0 8.0 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
VGS = 15 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 5.0 Vdc
Page 4
MOTOROLA CMOS LOGIC DATAMC14049B MC14050B
4
Figure 3. Ambient Temperature Power Derating
P
D
, MAXIMUM POWER DISSIPATION (mW)
PER PACKAGE
1200
1100
1000
900
825
800
740
700
600
500
400
300
200
100
0
175150125100755025
TA, AMBIENT TEMPERATURE (
°
C)
260 mW (L)
175 mW (P)
120 mW (D)
(L) CERAMIC
(P) PDIP
(D) SOIC
t
PHL
Figure 4. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
VSS8
1
C
L
V
out
V
in
#
#Invert on MC14049B only
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
90%
50%
10%
90%
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
PHL
t
THL
t
PHL
t
PLH
t
TLH
t
THL
OUTPUT
MC14049B
OUTPUT
MC14050B
INPUT
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14049B MC14050B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATAMC14049B MC14050B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14049B/D
*MC14049B/D*
◊
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