Datasheet MC14049UB Datasheet (ON Semiconductor)

查询MC14049UB供应商

MC14049UB

Hex Buffers

The MC14049UB hex inverter/buffer is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. This complementary MOS device finds primary use where low power dissipation and/or high noise immunity is desired. This device provides logic–level conversion using only one supply voltage, V VDD supply voltage for logic–level conversions. Two TTL/DTL Loads can be driven when the device is used as CMOS–to–TTL/DTL converters (VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA). Note that pins 13 and 16 are not connected internally on this device; consequently connections to these terminals will not affect circuit operation.

• High Source and Sink Currents

• High–to–Low Level Converter

• Supply Voltage Range = 3.0 V to 18 V

• Meets JEDEC UB Specifications

• V

can exceed V

IN

• Improved ESD Protection on All Inputs

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

V

out

I

out

P

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

All Packages: See Figure 4.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the V must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high–impedance circuit. For proper operation, the ranges V V

v 18 V and VSS v V

in

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input Voltage Range

in

Output Voltage Range

Input Current

in

Output Current

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C Lead Temperature

L

or VDD). Unused outputs must be left open.

SS

. The input–signal high level (VIH) can exceed the

DD

) (Note 2.)

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.) Plastic SOIC

(8–Second Soldering)

v VDD are recommended.

out

–0.5 to +18.0 V

–0.5 to VDD +0.5 V

±10 mA

+45 mA

825 740

260 °C

pin, only. Extra precautions

SS

mW

SS

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

TSSOP–16 DT SUFFIX

CASE 948F

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14049UBCP

AWLYYWW

1

16

14049U

AWLYWW

1

16

14

049U

ALYW

1

16

MC14049U

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14049UBCP PDIP–16 2000/Box MC14049UBD SOIC–16 2400/Box MC14049UBDR2 SOIC–16 2500/Tape & Reel MC14049UBDT TSSOP–16 96/Rail MC14049UBDTR2 TSSOP–16 2500/Tape & Reel MC14049UBF SOEIAJ–16 See Note 1.

v

MC14049UBFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14049UB/D

MC14049UB

V

DD

Î

PIN ASSIGNMENT

1

V

DD

OUT

2

A

3

IN

A

4

OUT

B

IN

B

OUT

6

C

7

IN

C

8

V

SS

NC = NO CONNECTION

16

NC OUT

15 14 13

125

11

10

F

IN

F

NC OUT

E

IN

E

OUT

D

9

IN

D

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

Output Voltage “0” Level

V

= VDD or 0

in

ОООООООО

“1” Level

= 0 or V

V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

(VOL = 0.4 Vdc) Sink

ОООООООО

(V

OL

(V

OL

ОООООООО

DD

= 4.5 Vdc) = 9.0 Vdc) = 13.5 Vdc)

“1” Level = 0.5 Vdc) = 1.0 Vdc) = 1.5 Vdc)

= 2.5 Vdc) Source = 9.5 Vdc) = 13.5 Vdc)

= 0.5 Vdc) = 1.5 Vdc)

Input Current Input Capacitance (Vin = 0) Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

(Dynamic plus Quiescent,

ОООООООО

Per Package)

ОООООООО

(C

= 50 pF on all outputs, all

L

buffers switching)

ОООООООО

(5.) (6.)

Symbol

ÎÎ

LOGIC DIAGRAM

MC14049UB

3

5

7

9

11

14 15

V Vdc

V

OL

V

OH

V

IL

V

IH

I

OH

I

OL

I

in

C

in

I

DD

I

T

5.0 10

Î

15

5.0 10

Î

15

Î

5.0 10

Î

15

Î

5.0 10

Î

15

Î

5.0 10

Î

15

5.0

Î

10 15

Î

15 —

5.0 10

Î

15

5.0 10

Î

15

Î

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

2

Max

0.05

ÎÎ

0.05 —

—

ÎÎ

—

ÎÎ

1.0

2.0

ÎÎ

2.5

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

— —

ÎÎ

± 0.1

20

1.0

2.0

ÎÎ

4.0

DD DD DD

MC14049UB

125_C

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

4.0

8.0

Î

12.5

Î

– 1.0 – 1.0

Î

– 3.0

2.6

Î

6.6 19

Î

— — —

—

Î

—

Max

0.05

Î

0.05

Î

± 1.0

Î

4

6

10

12

NC = PIN 13, 16 V

= PIN 8

SS

= PIN 1

V

DD

)

SS

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

4.0

8.0

Î

12.5

Î

– 1.6 – 1.6

Î

– 4.7

3.75

Î

10 30

Î

— — —

—

Î

—

– 55_C

Max

0.05

Î

0.05

Î

1.0

2.0

Î

2.5

Î

± 0.1

1.0

2.0

Î

4.0

Min

— —

ÎÎ

—

— — —

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

ÎÎ

— — —

4.0

8.0

ÎÎ

12.5

ÎÎ

– 1.25

– 1.3

ÎÎ

– 3.75

3.2

ÎÎ

8.0 24

ÎÎ

—

— —

—

ÎÎ

—

25_C

(4.)

Typ

0 0

Î

0

5.0 10

Î

15

Î

2.25

4.50

Î

6.75

Î

2.75

5.50

Î

8.25

Î

– 2.5 – 2.6

Î

– 10

6.0

Î

16 40

Î

±0.00001

10

0.002

0.004

Î

0.006

IT = (1.8 µA/kHz) f + I

ООООООООООООООО

IT = (3.5 µA/kHz) f + I IT = (5.3 µA/kHz) f + I

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

T

— — —

1.0

2.0

2.5

— — —

—

30 60

120

V

DD

V

SS

Î

mAdc

Î

mAdc

Î

Unit

Vdc

µAdc

pF

µAdc

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2

MC14049UB

Î

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(7.)

(C

= 50 pF, T

L

Output Rise Time

t

= (0.8 ns/pF) CL + 60 ns

TLH

= (0.3 ns/pF) CL + 35 ns

t

ООООООООООООО

TLH

t

= (0.27 ns/pF) CL + 26.5 ns

TLH

Output Fall Time

ООООООООООООО

t

= (0.3 ns/pF) CL + 25 ns

THL

= (0.12 ns/pF) CL + 14 ns

t

ООООООООООООО

THL

t

= (0.1 ns/pF) CL + 10 ns

THL

Propagation Delay Time

ООООООООООООО

t

= (0.38 ns/pF) CL + 61 ns

PLH

t

= (0.20 ns/pF) CL + 30 ns

PLH

ООООООООООООО

t

= (0.11 ns/pF) CL + 24.5 ns

PLH

Propagation Delay Time

ООООООООООООО

t

= (0.38 ns/pF) CL + 11 ns

PHL

= (0.12 ns/PF) CL + 9 ns

t

PHL

ООООООООООООО

t

= (0.11 ns/pF) CL + 4.5 ns

PHL

= 25_C)

A

Symbol

ÎÎÎ

t

TLH

ÎÎÎ

t

THL

ÎÎÎ

t

PLH

ÎÎÎ

t

PHL

ÎÎÎ

V

DD

Vdc

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

Min

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

(8.)

Typ

ÎÎ

100

50

ÎÎ

40

ÎÎ

40 20

ÎÎ

15

ÎÎ

80 40

ÎÎ

30

ÎÎ

30 15

ÎÎ

10

Max

ÎÎ

160 100

ÎÎ

60

ÎÎ

60 40

ÎÎ

30

ÎÎ

120

65

ÎÎ

50

ÎÎ

60 30

ÎÎ

20

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

18

Unit

Î

ns

Î

ns

Î

ns

Î

ns

Î

VDD = 15 Vdc

15

VDD = 10 Vdc

10

, OUTPUT VOLTAGE (Vdc)

out

V

VDD = 5 Vdc

5

–55°C

+125°C

1815105

, INPUT VOLTAGE (Vdc)

V

in

Figure 1. T ypical Voltage Transfer Characteristics versus Temperature

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3

MC14049UB

V

I

OUT

UT

SOU

CE

CU

NT

A

I

U

O

E

DISSI

ATION

V

dc) (m

–10

DD

1

I

OH

V

SS

8

0

OH

VDS = VOH – V

DD

160

VGS = 5.0 Vdc

120

DD

1

I

OL

V

VDD = V

OL

V

8

SS

RR

–20

R

VGS = 10 Vdc

–30

P

–40

,

OH

–50

–10 –8.0 –6.0 –4.0 –2.0 0

VGS = 15 Vdc

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

V

DS

MAXIMUM CURRENT LEVEL

80

MAXIMUM CURRENT LEVEL

40

, OUTPUT SINK CURRENT (mAdc)

OL

I

0

0 2.0 4.0 6.0 8.0 10

VGS = 5.0 Vdc

V

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

DS

Figure 2. T ypical Output Source Characteristics Figure 3. T ypical Output Sink Characteristics

DD

1

PULSE

GENERATOR

V

in

VSS8

20 ns 20 ns

INPUT

90% 50%

10%

t

PHL

OUTPUT

90% 50% 10%

t

THL

(mW)

P

R W

PER PACKAGE

M P M

X , M

D

P

1200

1100

1000

900 825 800

740 700

600 500 400 300 200 100

(P) PDIP

(D) SOIC

175 mW (P) 120 mW (D)

0

, AMBIENT TEMPERATURE (°C)

T

A

175150125100755025

Figure 4. Ambient Temperature Power Derating

Figure 5. Switching Time Test Circuit

and Waveforms

VGS = 15 Vdc

VGS = 10 Vdc

V

C

L

t

PLH

t

TLH

out

V

DD

V

SS

V

OH

V

OL

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4

–T–

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14049UB

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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5

–T–

0.10 (0.004)

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

MC14049UB

P ACKAGE DIMENSIONS

TSSOP–16 DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

16X REFK

0.10 (0.004) V

16

1

M

A

–V–

C

G

S

U

T

S

K

K1

9

J1

B

–U–

8

J

N

SECTION N–N

0.25 (0.010)

M

N

F

DETAIL E

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

–W–

G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

INCHESMILLIMETERS

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6

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14049UB

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

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MC14049UB

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

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MC14049UB/D

Datasheet MC14049UB Datasheet (ON Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual