Datasheet MC14046BFR2, MC14046BFL2, MC14046BFR1, MC14046BDWR2, MC14046BF Datasheet (MOTOROLA)

MOTOROLA CMOS LOGIC DATA

1

MC14046B

  

The MC14046B phase locked loop contains two phase comparators, a
voltage–controlled oscillator (VCO), source follower, and zener diode. The
comparators have two common signal inputs, PCAin and PCBin. Input PCA

in

can be used directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. The self–bias circuit
adjusts small voltage signals in the linear region of the amplifier. Phase
comparator 1 (an exclusive OR gate) provides a digital error signal PC1

out

,
and maintains 90° phase shift at the center frequency between PCAin and
PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2

out

and LD, and
maintains a 0° phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCO

out

whose
frequency is determined by the voltage of input VCOin and the capacitor and
resistors connected to pins C1A, C1B, R1, and R2. The source–follower
output SF

out

with an external resistor is used where the VC Oin signal is
needed but no loading can be tolerated. The inhibit input Inh, when high,
disables the VCO and source follower to minimize standby power
consumption. The zener diode can be used to assist in power supply
regulation.

Applications include FM and FSK modulation and demodulation, fre­quency synthesis and multiplication, frequency discrimination, tone decod­ing, data synchronization and conditioning, voltage–to–frequency
conversion and motor speed control.

• Buffered Outputs Compatible with MHTL and Low–Power TTL

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 to 18 V

• Pin–for–Pin Replacement for CD4046B

• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited

• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle

Limited

BLOCK DIAGRAM

PCA

in

PCB

in

VCO

in

INH

14

3
9

5

VDD = PIN 16

VSS = PIN 8

2 PC1

out

13 PC2

out

1LD
4 VCO

out

11 R1
12 R2
6C1

A

7C1

B

10 SF

out

15 ZENERV

SS

SELF BIAS

CIRCUIT

PHASE

COMPARATOR 1

PHASE

COMPARATOR 2

VOLTAGE

CONTROLLED

OSCILLATOR

(VCO)

SOURCE FOLLOWER



SEMICONDUCTOR TECHNICAL DATA

1

REV 4

 Motorola, Inc. 1997

10/97



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

R2

PC2

out

PCA

in

ZENER

V

DD

VCO

in

SF

out

R1

VCO

out

PCB

in

PC1

out

LD

V

SS

C1

B

C1

A

INH

MOTOROLA CMOS LOGIC DATAMC14046B

2

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Rating

Symbol

Value

Unit

DC Supply Voltage

V

DD

– 0.5 to + 18

Vdc

Input Voltage, All Inputs

V

in

– 0.5 to VDD + 0.5

Vdc

DC Input Current, per Pin

I

in

± 10

mAdc

Power Dissipation, per Package†

P

D

500

mW

Operating Temperature Range

T

A

– 55 to + 125

_

C

Storage Temperature Range

T

stg

– 65 to + 150

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C T o 125_C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

DD

– 55_C

25_C

125_C

Characteristic

Symbol

DD

Vdc

Min

Max

Min

Typ

Max

Min

Max

Unit

ООООООООО

Î

Output Voltage “0” Level

Vin = VDD or 0

Î

Î

V

OL

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

—
—
—

ÎÎ

Î

0
0
0

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ООООООООО

Î

“1” Level

Vin = 0 or V

DD

Î

Î

V

OH

Î

Î

5.0
10
15

ÎÎ

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

4.95

9.95

14.95

ÎÎ

Î

5.0
10
15

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

Input Voltage # “0” Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

Î

Î

Î

Î

V

IL

Î

Î

Î

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

2.25

4.50

6.75

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

Î

Î

Î

Î

V

IH

Î

Î

Î

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

ÎÎ

Î

ÎÎ

Î

2.75

5.50

8.25

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ООООООООО

Î

ООООООООО

Î

ООООООООО

Î

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

Î

Î

Î

Î

Î

Î

I

OH

Î

Î

Î

Î

Î

Î

5.0

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 1.2
– 0.25
– 0.62

– 1.8

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 1.0
– 0.2
– 0.5
– 1.5

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 1.7

– 0.36

– 0.9
– 3.5

Î

Î

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 0.7
– 0.14
– 0.35

– 1.1

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

mAdc

ООООООООО

Î

ООООООООО

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Î

Î

Î

I

OL

Î

Î

Î

5.0
10
15

ÎÎ

Î

ÎÎ

0.64

1.6

4.2

Î

Î

Î

—
—
—

Î

Î

Î

0.51

1.3

3.4

ÎÎ

Î

ÎÎ

0.88

2.25

8.8

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

0.36

0.9

2.4

Î

Î

Î

—
—
—

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

C

in

—

—

—

—

5.0

7.5

—

—

pF

ООООООООО

Î

ООООООООО

Î

Quiescent Current

(Per Package) Inh =

PCA

in

= VDD,

Zener = VCOin = 0 V, PCBin = V

DD

or 0 V, I

out

= 0 µA

Î

Î

Î

Î

I

DD

Î

Î

Î

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

5.0
10
20

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

0.005

0.010

0.015

Î

Î

Î

Î

5.0
10
20

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

150
300
600

Î

Î

Î

Î

µAdc

ООООООООО

Î

ООООООООО

Î

Total Supply Current†

(Inh = “0”, fo = 10 kHz, CL = 50 pF,
R1 = 1.0 MΩ, R2 = R RSF = ∞,
and 50% Duty Cycle)

Î

Î

Î

Î

I

T

Î

Î

Î

Î

5.0
10
15

ОООООООООООООООО

Î

ОООООООООООООООО

Î

IT = (1.46 µA/kHz) f + I

DD

IT = (2.91 µA/kHz) f + I

DD

IT = (4.37 µA/kHz) f + I

DD

Î

Î

Î

Î

mAdc

#Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc

2.0 Vdc min @ VDD = 10 Vdc

2.5 Vdc min @ VDD = 15 Vdc

†To Calculate Total Current in General:

IT [ 2.2 x V

DD

+ 1 x 10–3 (CL + 9) VDD f +

VCOin – 1.65

Ǔǒ

+

VDD – 1.35

3/4

R1 R2

VCOin – 1.65

3/4

+ 1.6 x

where: IT in µA, CL in pF, VCOin, VDD in Vdc, f in kHz, and

R1, R2, RSF in MΩ, CL on VCO

out

.

ǒ Ǔ

R

SF

1 x 10–1 V

DD

2

100% Duty Cycle of PCA

in

100

+ I

Q

Ǔǒ

MOTOROLA CMOS LOGIC DATA

3

MC14046B

ELECTRICAL CHARACTERISTICS* (C

L

= 50 pF, TA = 25°C)

V

Minimum

Maximum

Characteristic

Symbol

V

DD

Vdc

Device

Typical

Device

Units

ОООООООООООООО

Î

ОООООООООООООО

Î

Output Rise Time

t

TLH

= (3.0 ns/pF) CL + 30 ns

t

TLH

= (1.5 ns/pF) CL + 15 ns

t

TLH

= (1.1 ns/pF) CL + 10 ns

ÎÎ

Î

ÎÎ

Î

t

TLH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

—
—
—

ÎÎÎ

Î

ÎÎÎ

Î

180

90
65

ÎÎ

Î

ÎÎ

Î

350
150
110

Î

Î

Î

Î

ns

ОООООООООООООО

Î

ОООООООООООООО

Î

Output Fall Time

t

THL

= (1.5 ns/pF) CL + 25 ns

t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎ

Î

ÎÎ

Î

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

—
—
—

ÎÎÎ

Î

ÎÎÎ

Î

100

50
37

ÎÎ

Î

ÎÎ

Î

175

75
55

Î

Î

Î

Î

ns

PHASE COMPARATORS 1 and 2

ОООООООООООООО

Î

Input Resistance — PCA

in

ÎÎ

Î

R

in

ÎÎ

Î

5.0
10
15

ÎÎÎ

1.0

0.2

0.1

ÎÎÎ

Î

2.0

0.4

0.2

ÎÎ

Î

—
—
—

Î

Î

MΩ

— PCB

in

R

in

15

150

1500

—

MΩ

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Input Sensitivity

AC Coupled — PCA

in

C series = 1000 pF, f = 50 kHz

ÎÎ

Î

ÎÎ

Î

V

in

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

—
—
—

ÎÎÎ

Î

ÎÎÎ

Î

200
400
700

ÎÎ

Î

ÎÎ

Î

300
600

1050

Î

Î

Î

Î

mV p–p

ОООООООООООООО

Î

DC Coupled — PCAin, PCB

in

ÎÎ

Î

—

ÎÎ

Î

5 to 15

ООООООООО

Î

See Noise Immunity

Î

Î

ОООООООООООООООООООООООООООООООО

VOLTAGE CONTROLLED OSCILLATOR (VCO)

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Frequency

(VCOin = VDD, C1 = 50 pF
R1 = 5.0 kΩ, and R2 = ∞)

ÎÎ

Î

ÎÎ

Î

f

max

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

0.5

1.0

1.4

ÎÎÎ

Î

ÎÎÎ

Î

0.7

1.4

1.9

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

MHz

ОООООООООООООО

Î

Temperature — Frequency Stability

(R2 = ∞ )

ÎÎ

Î

—

ÎÎ

Î

5.0
10
15

ÎÎÎ

—
—
—

ÎÎÎ

Î

0.12

0.04

0.015

ÎÎ

Î

—
—
—

Î

Î

%/_C

ОООООООООООООО

Î

ОООООООООООООО

Î

Linearity (R2 = ∞ )

(VCOin = 2.5 V ± 0.3 V , R1 > 10 kΩ)
(VCOin = 5.0 V ± 2.5 V , R1 > 400 kΩ )
(VCOin = 7.5 V ± 5.0 V , R1 ≥ 1000 kΩ)

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

—
—
—

ÎÎÎ

Î

ÎÎÎ

Î

1.0

1.0

1.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

%

Output Duty Cycle

—

5 to 15

—

50

—

%

Input Resistance — VCO

in

R

in

15

150

1500

—

MΩ

SOURCE–FOLLOWER

ОООООООООООООО

Î

Offset Voltage

(VCOin minus SF

out

, RSF > 500 kΩ)

ÎÎ

Î

—

ÎÎ

Î

5.0
10
15

ÎÎÎ

—
—
—

ÎÎÎ

Î

1.65

1.65

1.65

ÎÎ

Î

2.2

2.2

2.2

Î

Î

V

ОООООООООООООО

Î

ОООООООООООООО

Î

Linearity

(VCOin = 2.5 V ± 0.3 V , RSF > 50 kΩ)
(VCOin = 5.0 V ± 2.5 V , RSF > 50 kΩ)
(VCOin = 7.5 V ± 5.0 V , RSF > 50 kΩ)

ÎÎ

Î

ÎÎ

Î

—

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎÎ

ÎÎÎ

—
—
—

ÎÎÎ

Î

ÎÎÎ

Î

0.1

0.6

0.8

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

%

ZENER DIODE

Zener Voltage (Iz = 50 µA)

V

Z

—

6.7

7.0

7.3

V

Dynamic Resistance (Iz = 1.0 mA)

R

Z

—

—

100

—

Ω

*The formula given is for the typical characteristics only.

MOTOROLA CMOS LOGIC DATAMC14046B

4

Figure 1. Phase Comparators State Diagrams

PHASE COMPARATOR 1

Input Stage

PCA

in

XX

PCB

in

00 01

11 10

PC1

out

01

PHASE COMPARATOR 2

Input Stage

PCA

in

XX

PCB

in

PC2

out

01

3–State

Output Disconnected

LD

(Lock Detect)

001

Refer to Waveforms in Figure 3.

00

01 10

11

00

10 01

11

00

01 10

11

Characteristic

Using Phase Comparator 1

Using Phase Comparator 2

ОООООООООО

Î

No signal on input PCAin.

ОООООООООО

Î

VCO in PLL system adjusts to center
frequency (f0).

ОООООООООО

Î

VCO in PLL system adjusts to minimum
frequency (f

min

).

ОООООООООО

Î

Phase angle between PCAin and PCBin.

ОООООООООО

Î

90° at center frequency (f0), approaching 0

_

and 180° at ends of lock range (2fL)

ОООООООООО

Î

Always 0_ in lock (positive rising edges).

ОООООООООО

Î

Locks on harmonics of center frequency.

ОООООООООО

Î

Yes

ОООООООООО

Î

No

Signal input noise rejection.

High

Low

ОООООООООО

Î

Lock frequency range (2fL).

ООООООООООООООООООООО

Î

The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = f

max

– f

min

.

ОООООООООО

Î

Capture frequency range (2fC).

ООООООООООООООООООООО

Î

The frequency range of the input signal on which the loop will lock if it was initially
out of lock.

ООООООООООÎОООООООООО

Î

Depends on low–pass filter characteristics
(see Figure 3). fC v f

L

ОООООООООО

Î

fC = f

L

ОООООООООО

Î

Center frequency (f0).

ООООООООООООООООООООО

Î

The frequency of VCO

out

, when VCOin = 1/2 V

DD

ОООООООООО

Î

ОООООООООО

Î

ОООООООООО

Î

ОООООООООО

Î

ОООООООООО

Î

ОООООООООО

Î

VCO output frequency (f).

Note: These equations are intended to be
a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than ± 20%.

ООООООООООООООООООООО

Î

ООООООООООООООООООООО

Î

ООООООООООООООООООООО

Î

ООООООООООООООООООООО

Î

ООООООООООООООООООООО

Î

ООООООООООООООООООООО

Î

Where: 10K v R1 v 1 M

10K v R2 v 1 M
100pF v C1 v .01 µF

Figure 2. Design Information

+ f

min

f

min

=(V

CO

input = VSS)

R2(C1 + 32 pF)

1

f

max

=

R1(C1 + 32 pF)

1

(VCO input = VDD)

MOTOROLA CMOS LOGIC DATA

5

MC14046B

Typical Low–Pass Filters

NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for

CC should be such that the corner frequency of this network does not significantly affect ωn. In Figure B, the ratio of R3 to R4 sets the
damping, R4 ^ (0.1)(R3) for optimum results.

Figure 3. General Phase–Locked Loop Connections and Waveforms

Waveforms

Note: for further information, see:

(1) F. Gardner, “Phase–Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase–Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase–Lock Loop Design Fundamentals”, AN–535, Motorola Inc.
(4) A. B. Przedpelski, “Phase–Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.

PCA

in

@ FREQUENCY f

′

PCB

in

14

3

PHASE

COMPARATOR

EXTERNAL
LOW–PASS

FILTER

VCO

2 OR 13
PC1

out

OR

PC2

out

VCO

in

9

9

10

4

EXTERNAL

÷

N

COUNTER

R1 R2

11 12 6 7

CIACI

B

CI

SF

out

R

SF

VCO

out

@ FREQUENCY Nf

′

= f

(a)
INPUT

R3

OUTPUT

C2

2fC[

1

p

2pf

L

R3 C2

Ǹ

(a)
INPUT

R3

OUTPUT

R4

C2

Typically:
R4C2+

6N

f

max

–

N

2

pD

f

(R3)

3,000W)C2+

100NDf

f

max

2

–R4C

2

∆f = f

max

– f

min

Definitions: N = Total division ratio in feedback loop

Kφ = VDD/π for Phase Comparator 1
Kφ = VDD/4 π for Phase Comparator 2

K

VCO

+

2pDf

VCO

VDD–2V

2pf

r

10

for a typical design ωn

^

(at phase detector input)

ζ ^ 0.707

LOW–PASS FILTER

Filter A Filter B

wn+

KfK

VCO

NR3C

2

Ǹ

z

+

N

w

n

2KfK

VCO

F(s)

+

1

R3C2S)1

wn+

KfK

VCO

NC2(R3)

R

4

)

Ǹ

z+0.5

wn(R3C2)

N

KfK

VCO

)

F(s)

+

R3C2S)1

S(R3C2)

R4C2))1

PCA

in

PCB

in

PC1

out

VCO

in

V

DD

V

SS

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

PCA

in

PCB

in

PC2

out

VCO

in

LD

V

DD

V

SS

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OL

V

OH

Phase Comparator 1 Phase Comparator 2

SOURCE

FOLLOWER

MOTOROLA CMOS LOGIC DATAMC14046B

6

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

____

16 9

18

MOTOROLA CMOS LOGIC DATA

7

MC14046B

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC WIDE PACKAGE

CASE 751G–03

ISSUE B

D

14X

B16X

SEATING
PLANE

S

A

M

0.25 B

S

T

16 9

81

h X 45

_

M

B

M

0.25

H8X

E

B

A

e

T

A1

A

L

C

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

DIM MIN MAX

MILLIMETERS

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q

0 7

__

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

MC14046B/D

◊

Mfax is a trademark of Motorola, Inc.

How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488

Customer Focus Center: 1–800–521–6274
Mfax: [e-mail] – TOUCHTONE 1–602–244–6609 ASIA /PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Moto rola Fax Ba ck System – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/