Datasheet MC14042BDR2, MC14042BCP, MC14042BD, MC14042BF, MC14042BFEL Datasheet (MOTOROLA)

MC14042B

Quad Transparent Latch

The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q

during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.

• Buffered Data Inputs

• Common Clock

• Clock Polarity Control

• Q and Q Outputs

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

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16

PDIP–16

P SUFFIX

CASE 648

16

SOIC–16

D SUFFIX

CASE 751B

MARKING

DIAGRAMS

MC14042BCP

AWLYYWW

1

14042B

AWLYWW

1

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C Lead Temperature

L

SS

or VDD). Unused outputs must be left open.

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

16

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14042B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14042BCP PDIP–16 2000/Box MC14042BD SOIC–16 2400/Box MC14042BDR2 SOIC–16 2500/Tape & Reel MC14042BF SOEIAJ–16 See Note 1. MC14042BFEL SOEIAJ–16 See Note 1. MC14042BFR1 SOEIAJ–16 See Note 1. MC14042BFR2 SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14042B/D

MC14042B

PIN ASSIGNMENT

Q3 Q0 Q0 D0

CLOCK

POLARITY

D1

V

1 2 3 4

6 7 8

SS

16 15 14 13 125 11 10

TRUTH TABLE

Clock Polarity Q

0 0 Data 1 0 Latch 1 1 Data 0 1 Latch

LOGIC DIAGRAM

V

DD

3

Q D3 D2

Q

2 Q2 Q1 Q1

9

CLOCK

POLARITY

= PIN 16

V

DD

V

= PIN 8

SS

D0

5

6

D1

D2

D3

4

7

13

14

LATCH

1

LATCH

2

LATCH

3

LATCH

4

Q0

2

0

Q

3

Q1

10

1

Q

9

Q2

11

Q

2

12

Q3

1

Q

3

15

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2

MC14042B

V

DD

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Output Voltage “0” Level

= VDD or 0

V

in

ОООООООО

“1” Level

V

= 0 or V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

ОООООООО

(V

OH

DD

= 4.5 or 0.5 Vdc) = 9.0 or 1.0 Vdc) = 13.5 or 1.5 Vdc)

“1” Level = 0.5 or 4.5 Vdc) = 1.0 or 9.0 Vdc) = 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source = 4.6 Vdc) = 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

= 50 pF on all outputs all

(C

L

ОООООООО

buffers switching)

(5.) (6.)

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

ÎÎ

V

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

ÎÎ

I

DD

ÎÎ

I

ÎÎ

Vdc

5.0 10

Î

15

5.0 10

Î

15

IL

Î

5.0 10

Î

15

IH

Î

5.0 10

Î

15

Î

5.0

Î

10

Î

15

5.0 10

Î

15 15

in

—

Î

5.0 10

Î

15

T

5.0

Î

10 15

Î

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2 — —

Î

— —

Î

—

ООООООООООООООО

SS

– 55_C

)

Max

0.05

Î

0.05

Î

1.5

3.0

Î

4.0

Î

± 0.1

Î

1.0

2.0

Î

4.0

25_C

Min

— —

ÎÎ

—

— — —

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

ÎÎ

— — —

— — — —

— — —

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4 —

—

ÎÎ

— —

ÎÎ

— IT = (1.0 µA/kHz) f + I

IT = (2.0 µA/kHz) f + I IT = (3.0 µA/kHz) f + I

(4.)

Typ

0 0

Î

0

5.0 10

Î

15

Î

2.25

4.50

Î

6.75

Î

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

– 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.002

0.004

Î

0.006

Max

0.05

ÎÎ

0.05 —

—

ÎÎ

—

ÎÎ

1.5

3.0

ÎÎ

4.0

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

—

ÎÎ

—

± 0.1

7.5

ÎÎ

1.0

2.0

ÎÎ

4.0

DD DD DD

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 1.7

– 0.36

Î

– 0.9

Î

– 2.4

0.36

0.9

Î

2.4 — —

Î

— —

Î

—

125_C

Max

0.05

Î

0.05

Î

± 1.0

Î

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

T

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

30 60

120

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

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3

MC14042B

Î

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

Characteristic

Output Rise and Fall Time

t

, t

TLH

ООООООООООООО

t

TLH

t

ООООООООООООО

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time, D to Q, Q

t

, t

PLH

ООООООООООООО

t

PLH

t

PLH

ООООООООООООО

= (1.7 ns/pF) CL + 135 ns

PHL

, t

= (0.66 ns/pF) CL + 57 ns

PHL

, t

= (0.5 ns/pF) CL + 35 ns

PHL

Propagation Delay Time, Clock to Q, Q

t

, t

PLH

ООООООООООООО

t

PLH

t

PLH

ООООООООООООО

= (1.7 ns/pF) CL + 135 ns

PHL

, t

= (0.66 ns/pF) CL + 57 ns

PHL

, t

= (0.5 ns/pF) CL + 35 ns

PHL

Clock Pulse Width

ООООООООООООО

Clock Pulse Rise and Fall Time

ООООООООООООО

Hold Time

ООООООООООООО

Setup Time

ООООООООООООО

= 25_C)

A

Symbol

t

TLH

t

THL

ÎÎÎ

t

PLH

t

PHL

ÎÎÎ

t

PLH

t

PHL

ÎÎÎ

t

WH

ÎÎÎ

t

TLH

t

THL

ÎÎÎ

t

h

ÎÎÎ

t

su

ÎÎÎ

V

DD

Min

Typ

(8.)

Max

,

5.0

ÎÎ

10 15

ÎÎ

—

ÎÎ

— —

ÎÎ

100

ÎÎ

50 40

ÎÎ

200

ÎÎ

100

80

ÎÎ

,

5.0

ÎÎ

10 15

ÎÎ

—

ÎÎ

— —

ÎÎ

220

ÎÎ

90 60

ÎÎ

440

ÎÎ

180 120

ÎÎ

,

5.0

ÎÎ

10 15

ÎÎ

5.0

ÎÎ

10 15

ÎÎ

—

ÎÎ

— —

ÎÎ

300

ÎÎ

100

80

ÎÎ

220

ÎÎ

90 60

ÎÎ

150

ÎÎ

50 40

ÎÎ

440

ÎÎ

180 120

ÎÎ

—

ÎÎ

— —

ÎÎ

,

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

—

ÎÎ

— —

ÎÎ

100

50

ÎÎ

40

ÎÎ

50 30

ÎÎ

25

—

ÎÎ

— —

ÎÎ

50 25

ÎÎ

20

ÎÎ

0 0

ÎÎ

0

15

ÎÎ

5.0

4.0

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

Î

no

Î

ns

Î

ns

Î

µs

Î

ns

Î

ns

Î

5 6

PULSE

GENERATOR 1

4

7 13 14

For Power Dissipation test, each output is loaded with capacitance C

.

L

Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

V

DD

16

CLOCK POLARITY D0 D1 D2 D3 Q

8

V

SS

Q0 Q Q1 Q Q2 Q

Q3

2 3

0

10 9

1

11 12

2

1 15

3

(Data to Output)

DATA INPUT

Q OUTPUT

OUTPUT

Q

1

f

20 ns 20 ns

90%

50%

10%

t

PLH

10%

90%

t

10%

PHL

t

TLH

THL

50%

t

PHL

t

TLH

THL

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4

MC14042B

16

V

DD

20* ns 20 ns

CLOCK INPUT

P.G. 1

DATA INPUT

P.G. 2

Q OUTPUT

PULSE

GENERATOR 1

PULSE

GENERATOR 2

5 6

4

7 13 14

NOTE: CL connected to output under test.

90%

50%

10%

t

WH

20 ns

90%

t

su

t

PLH

90%

50%

10%

CLOCK POLARITY

D0 D1 D2 D3 Q

VSS8

50%

t

h

Q0 Q Q1 Q Q2 Q Q3

2

0

3 10

1

9 11

2

12 1

3

15

*Input clock rise time is 20 ns except for maximum rise time test.

Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)

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5

–T–

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14042B

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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6

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14042B

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

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7

MC14042B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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MC14042B/D

Datasheet MC14042BDR2, MC14042BCP, MC14042BD, MC14042BF, MC14042BFEL Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual