Datasheet MC14040BFL1, MC14040BFL2, MC14040BFR1, MC14040BFR2, MC14040BDT Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14040B/D

MC14040B

12-Bit Binary Counter

The MC14040B 12–stage binary counter is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple–carry binary counter. The device
advances the count on the negative–going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency–driving circuits.

• Fully Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Common Reset Line

• Pin–for–Pin Replacement for CD4040B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14040BCP PDIP–16 2000/Box
MC14040BD SOIC–16 2400/Box
MC14040BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14040BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14040B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14040B

AWLYWW

MC14040BDT TSSOP–16 96/Rail
MC14040BF SOEIAJ–16 See Note 1.
MC14040BFEL SOEIAJ–16 See Note 1.

TSSOP–16
DT SUFFIX

CASE 948F

14

040B

ALYW

1

16

MC14040B

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2

TRUTH TABLE

Clock Reset Output State

0 No Change
0 Advance to next state

X 1 All Outputs are low

X = Don’t Care

LOGIC DIAGRAM

CLOCK

10

RESET

11

Q1 Q2 Q3 Q10 Q11 Q12

976 14151

Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2

Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12

V

DD

= PIN 16

V

SS

= PIN 8

CQ

R

CQ

CQ

R

CQ

CQ

R

CQ

CQ

R

CQ

CQ

R

CQ

CQ

R

C

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q9

Q8

Q10

Q11

V

DD

Q1

C

R

Q7

Q5

Q6

Q12

V

SS

Q2

Q3

Q4

MC14040B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

“1” Level

V

in

= 0 or V

DD

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

Î

Î

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

Î

Î

mAdc

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

I

OL

Î

Î

5.0
10
15

Î

Î

0.64

1.6

4.2

Î

Î

—
—
—

ÎÎ

Î

0.51

1.3

3.4

Î

Î

0.88

2.25

8.8

ÎÎ

Î

—
—
—

Î

Î

0.36

0.9

2.4

Î

Î

—
—
—

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ОООООООО

Î

Input Capacitance

(V

in

= 0)

ÎÎ

Î

C

in

Î

Î

—

Î

Î

—

Î

Î

—

ÎÎ

Î

—

Î

Î

5.0

ÎÎ

Î

7.5

Î

Î

—

Î

Î

—

Î

Î

pF

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

I

DD

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

5.0
10
20

ÎÎ

Î

—
—
—

Î

Î

0.005

0.010

0.015

ÎÎ

Î

5.0
10
20

Î

Î

—
—
—

Î

Î

150
300
600

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.42 µA/kHz) f + I

DD

IT = (0.85 µA/kHz) f + I

DD

IT = (1.43 µA/kHz) f + I

DD

Î

Î

Î

Î

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14040B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

ООООООООООООО

Î

Characteristic

ÎÎÎ

Î

Symbol

ÎÎ

Î

V

DD

Vdc

ÎÎ

Î

Min

ÎÎ

Î

Typ

(8.)

ÎÎ

Î

Max

Î

Î

Unit

ООООООООООООО

Î

Output Rise and Fall Time

T

TLH

, T

THL

= (1.5 ns/pF) CL + 25 ns

T

TLH

, T

THL

= (0.75 ns/pF) CL + 12.5 ns

T

TLH

, T

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

100

50
40

ÎÎ

Î

200
100

80

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time
Clock to Q1

t

PHL

, t

PLH

= (1.7 ns/pF) CL + 315 ns

t

PHL

, t

PLH

= (0.66 ns/pF) CL + 137 ns

t

PHL

, t

PLH

= (0.5 ns/pF) CL + 95 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

260
115

80

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

520
230
160

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Clock to Q12

t

PHL

, t

PLH

= (1.7 ns/pF) CL + 2415 ns

t

PHL

, t

PLH

= (0.66 ns/pF) CL + 867 ns

t

PHL

, t

PLH

= (0.5 ns/pF) CL + 475 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

1625

720
500

ÎÎ

Î

ÎÎ

Î

3250
1440
1000

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time
Reset to Q

n

t

PHL

= (1.7 ns/pF) CL + 485 ns

t

PHL

= (0.86 ns/pF) CL + 182 ns

t

PHL

= (0.5 ns/pF) CL + 145 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

370
155
115

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

740
310
230

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Clock Pulse Width

ÎÎÎ

Î

ÎÎÎ

Î

t

WH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

385
150
115

ÎÎ

Î

ÎÎ

Î

140

55
38

ÎÎ

Î

ÎÎ

Î

—

—

—

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Frequency

ÎÎÎ

Î

f

cl

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

2.1

7.0

10.0

ÎÎ

Î

1.5

3.5

4.5

Î

Î

MHz

ООООООООООООО

Î

Clock Rise and Fall Time

ÎÎÎ

Î

t

TLH

, t

THL

ÎÎ

Î

5.0
10
15

ОООООООО

Î

No Limit

Î

Î

ns

ООООООООООООО

Î

Reset Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

960
360
270

ÎÎ

Î

320
120

80

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Reset Removal Time

ÎÎÎ

Î

ÎÎÎ

Î

t

rem

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

130

50
30

ÎÎ

Î

ÎÎ

Î

65
25
15

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit

and Waveform

Figure 2. Switching Time Test Circuit

and Waveforms

PULSE

GENERATOR

PULSE

GENERATOR

500 µF

0.01 µF
CERAMIC

V

DD

V

SS

C

L

C

L

C

L

I

D

Q1
Q2

Q

n

C

R

20 ns 20 ns

V

DD

V

SS

90%
50%
10%

CLOCK

50% DUTY CYCLE

V

DD

V

SS

C

L

C

L

C

L

Q1
Q2

Q

n

C

R

20 ns 20 ns

CLOCK

90%

50%

10%

t

WH

t

PHL

t

PLH

Q

90%
50%
10%

t

TLHtTHL

MC14040B

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5

Figure 3. Timing Diagram

CLOCK

RESET

Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

Q9
Q10
Q11
Q12

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

APPLICATIONS INFORMATION

TIME–BASE GENERATOR

A 60 Hz sinewave obtained through a 1.0 Megohm
resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting

outputs Q5, Q10, Q11, and Q12 division by 3600 is
accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.

V

DD

V

SS

120 Vac

60 Hz

1.0 M

≥ 20 pF

MC14040B

C

R Q12

Q11

Q10

Q5

1/2

MC14012B

1/2

MC14012B

1.0 PULSE/MINUTE
OUTPUT

MC14040B

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6

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14040B

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7

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14040B

http://onsemi.com

8

P ACKAGE DIMENSIONS

TSSOP–16
DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

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