Datasheet MC14040BCL, MC14040BCP, MC14040BD Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATAMC14040B

150

  

The MC14040B 12–stage binary c ounter i s constructed with MOS P–channel a nd N –channel e nhancement m ode devices i n a single monolithic structure. This part is designed with an input wave shaping circuit and 12 stages of ripple–carry binary counter. The device advances the count on the negative–going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency–driving circuits.

• Fully Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Common Reset Line

• Pin–for–Pin Replacement for CD4040B

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

lin, l

out

Input or Output Current (DC or Transient), per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM

CLOCK

10

RESET

11

Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1

Q4 = PIN 5 Q5 = PIN 3 Q6 = PIN 2

Q7 = PIN 4 Q8 = PIN 13 Q9 = PIN 12

VDD = PIN 16 VSS = PIN 8

C Q

R

C Q

R

C Q

R

C Q

R

C Q

R

C Q

R

C



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



  



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

TRUTH TABLE

Clock Reset Output State

0 No Change 0 Advance to next state

X 1 All Outputs are low

X = Don’t Care

MOTOROLA CMOS LOGIC DATA

151

MC14040B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

V

IL

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

V

IH

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

I

OH

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2

– 0.88

– 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

I

OL

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

5.0

7.5

—

ÎÎÎ

—

pF

Quiescent Current

(Per Package)

I

DD

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

I

T

5.0 10 15

IT = (0.42 µA/kHz) f + I

DD

IT = (0.85 µA/kHz) f + I

DD

IT = (1.43 µA/kHz) f + I

DD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q9

Q8

Q10

Q11

V

DD

Q1

C

R

Q7

Q5

Q6

Q12

V

SS

Q2

Q3

Q4

MOTOROLA CMOS LOGIC DATAMC14040B

152

SWITCHING CHARACTERISTICS (C

L

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

T

TLH

, T

THL

= (1.5 ns/pF) CL + 25 ns

T

TLH

, T

THL

= (0.75 ns/pF) CL + 12.5 ns

T

TLH

, T

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ

t

TLH

,

t

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

80

ns

Propagation Delay Time Clock to Q1

t

PHL

, t

PLH

= (1.7 ns/pF) CL + 315 ns

t

PHL

, t

PLH

= (0.66 ns/pF) CL + 137 ns

t

PHL

, t

PLH

= (0.5 ns/pF) CL + 95 ns

ÎÎÎÎ

t

PLH

,

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

260 115

80

520 230 160

ns

Clock to Q12

t

PHL

, t

PLH

= (1.7 ns/pF) CL + 2415 ns

t

PHL

, t

PLH

= (0.66 ns/pF) CL + 867 ns

t

PHL

, t

PLH

= (0.5 ns/pF) CL + 475 ns

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

1625

720 500

3250 1440 1000

ns

Propagation Delay Time Reset to Q

n

t

PHL

= (1.7 ns/pF) CL + 485 ns

t

PHL

= (0.86 ns/pF) CL + 182 ns

t

PHL

= (0.5 ns/pF) CL + 145 ns

ÎÎÎÎ

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

370 155 115

740 310 230

ns

Clock Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

385 150 115

140

55 38

—

ns

Clock Pulse Frequency

ÎÎÎÎ

f

cl

5.0 10 15

ÎÎÎÎ

— — —

2.1

7.0

10.0

1.5

3.5

4.5

MHz

Clock Rise and Fall Time

ÎÎÎÎ

t

TLH

, t

THL

5.0 10 15

ОООООООООО

No Limit

ns

Reset Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

960 360 270

320 120

80

— — —

ns

Reset Removal Time

ÎÎÎÎ

t

rem

5.0 10 15

ÎÎÎÎ

130

50 30

65 25 15

— — —

ns

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit

and Waveform

Figure 2. Switching Time Test Circuit

and Waveforms

PULSE

GENERATOR

PULSE

GENERATOR

500

µ

F

0.01 µF CERAMIC

V

DD

V

SS

C

L

C

L

C

L

I

D

Q1 Q2 Q

n

C

R

20 ns 20 ns

V

DD

V

SS

90% 50% 10%

CLOCK

50% DUTY CYCLE

V

DD

V

SS

C

L

C

L

C

L

Q1 Q2 Q

n

C

R

20 ns 20 ns

CLOCK

90%

50%

10%

t

WH

t

PHL

t

PLH

Q

90% 50% 10%

t

TLHtTHL

MOTOROLA CMOS LOGIC DATA

153

MC14040B

Figure 3. Timing Diagram

CLOCK

RESET

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

Q9 Q10 Q11 Q12

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

APPLICATIONS INFORMATION

TIME–BASE GENERATOR

A 60 Hz sinewave obtained through a 1.0 Megohm resistor connected directly to a standard 120 Vac p ower l ine is applied to the clock i nput of the MC14040B. By selecting

outputs Q5, Q10, Q11, and Q12 division by 3600 is accomplished. The MC14012B decodes the counter outputs, produces a single output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute.

V

DD

V

SS

120 Vac

60 Hz

1.0 M

≥

20 pF

MC14040B

C

R Q12

Q11

Q10

Q5

1/2

MC14012B

1/2

MC14012B

1.0 PULSE/MINUTE OUTPUT

MOTOROLA CMOS LOGIC DATAMC14040B

154

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

155

MC14040B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

_ _ _ _

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MC14040B/D

*MC14040B/D*

◊

Datasheet MC14040BCL, MC14040BCP, MC14040BD Datasheet (Motorola)

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