The MC14040B 12−stage binary counter is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple−carry binary counter. The device
advances the count on the negative−going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency−driving circuits.
Features
• Fully Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Common Reset Line
• Pin−for−Pin Replacement for CD4040B
• Pb−Free Packages are Available*
http://onsemi.com
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
16
1
16
MARKING
DIAGRAMS
MC14040BCP
AWLYYWW
14040B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
DC Supply Voltage Range−0.5 to +18.0V
DD
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation, per Package
D
Ambient Temperature Range−55 to +125°C
A
Storage Temperature Range−65 to +150°C
stg
Lead Temperature
L
SS
SS
ParameterValueUnit
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
(Vin or V
or VDD). Unused outputs must be left open.
) VDD.
out
)
SS
−0.5 to VDD + 0.5V
±10mA
500mW
260°C
and V
in
should be constrained
out
16
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
A= Assembly Location
WL, L= Wafer Lot
YY, Y= Year
WW, W = Work Week
14
040B
ALYW
1
16
MC14040B
AWLYWW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 6
1Publication Order Number:
MC14040B/D
Page 2
PIN ASSIGNMENT
MC14040B
RESET
CLOCK
11
Q12
Q6
Q5
Q7
Q4
Q3
Q2
V
1
2
3
4
6
7
8
SS
V
16
DD
Q11
15
Q10
14
Q8
13
Q9
125
11
R
10
C
9
Q1
ClockResetOutput State
X1All Outputs are low
X = Don’t Care
TRUTH TABLE
0No Change
0Advance to next state
LOGIC DIAGRAM
Q1Q2Q3Q10Q11Q12
97614151
10
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
C
R
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
V
DD
V
SS
= PIN 16
= PIN 8
ORDERING INFORMATION
DevicePackageShipping
MC14040BCPPDIP−16500 Units / Rail
MC14040BCPGPDIP−16
(Pb−Free)
MC14040BDSOIC−1648 Units / Rail
MC14040BDGSOIC−16
(Pb−Free)
MC14040BDR2SOIC−162500 Units / Tape & Reel
MC14040BDR2GSOIC−16
(Pb−Free)
MC14040BDTTSSOP−16*96 Units / Rail
MC14040BDTR2TSSOP−16*2500 Units / Tape & Reel
MC14040BFELSOEIAJ−162000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
500 Units / Rail
48 Units / Rail
2500 Units / Tape & Reel
†
http://onsemi.com
2
Page 3
MC14040B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
Characteristic
ОООООООО
Output Voltage“0” Level
V
= VDD or 0
in
ОООООООО
“1” Level
V
= 0 or V
in
ОООООООО
DD
Input Voltage“0” Level
(V
= 4.5 or 0.5 Vdc)
ОООООООО
O
= 9.0 or 1.0 Vdc)
(V
O
ОООООООО
= 13.5 or 1.5 Vdc)
(V
O
“1” Level
= 0.5 or 4.5 Vdc)
(V
ОООООООО
O
(V
= 1.0 or 9.0 Vdc)
O
ОООООООО
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
ОООООООО
ОООООООО
ОООООООО
(V
OH
(V
OH
(V
OH
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
ОООООООО
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
= 0)
in
ОООООООО
Quiescent Current
(Per Package)
ОООООООО
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
ОООООООО
Per Package)
ОООООООО
(C
= 50 pF on all outputs, all
L
buffers switching)
ОООООООО
Symbol
ÎÎ
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
ÎÎ
I
OL
ÎÎ
I
in
C
in
ÎÎ
I
DD
ÎÎ
I
T
ÎÎ
ÎÎ
ÎÎ
DD
Vdc
Î
5.0
10
15
Î
5.0
10
Î
15
5.0
Î
10
Î
15
5.0
Î
10
Î
15
5.0
Î
5.0
Î
10
15
Î
5.0
10
Î
15
15
−
Î
5.0
10
Î
15
5.0
10
Î
15
Î
Î
Min
Î
Î
4.95
9.95
Î
14.95
Î
Î
3.5
Î
7.0
Î
11
– 3.0
Î
– 0.64
Î
– 1.6
– 4.2
Î
0.64
1.6
Î
4.2
Î
Î
ООООООООООООООО
ООООООООООООООО
ООООООООООООООО
− 55C
−
−
−
−
−
−
−
−
−
−
−
SS
)
Max
Î
0.05
0.05
0.05
Î
Î
1.5
Î
3.0
Î
4.0
Î
Î
Î
Î
Î
Î
± 0.1
Î
5.0
Î
—
—
—
10
20
−
−
−
−
−
−
−
−
−
−
−
25C
Min
ÎÎ
−
−
−
ÎÎ
4.95
9.95
ÎÎ
14.95
−
ÎÎ
−
ÎÎ
−
3.5
ÎÎ
7.0
ÎÎ
11
– 2.4
ÎÎ
– 0.51
ÎÎ
– 1.3
– 3.4
ÎÎ
0.51
1.3
ÎÎ
3.4
−
−
ÎÎ
−
−
ÎÎ
−
Typ
(Note 2)
Î
0
0
0
Î
5.0
10
Î
15
2.25
Î
4.50
Î
6.75
2.75
Î
5.50
Î
8.25
– 4.2
Î
– 0.88
Î
– 2.25
– 8.8
Î
0.88
2.25
Î
8.8
±0.00001
5.0
Î
0.005
0.010
Î
0.015
IT = (0.42 A/kHz) f + I
IT = (0.85 A/kHz) f + I
IT = (1.43 A/kHz) f + I
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
−
−
ÎÎ
−
1.5
ÎÎ
3.0
ÎÎ
4.0
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
± 0.1
7.5
ÎÎ
5.0
10
ÎÎ
20
DD
DD
DD
Min
Î
−
−
−
Î
4.95
9.95
Î
14.95
−
Î
−
Î
−
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
Î
– 0.9
– 2.4
Î
0.36
0.9
Î
2.4
−
−
Î
−
−
Î
−
125C
Max
Î
0.05
0.05
0.05
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
Î
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk
I
T(CL
where: I
is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
T
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
150
300
600
Unit
Î
Vdc
Î
Vdc
Î
Vdc
Î
Î
Vdc
Î
Î
mAdc
Î
Î
Î
mAdc
Î
Adc
pF
Î
Adc
Î
Adc
Î
Î
Î
http://onsemi.com
3
Page 4
MC14040B
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
SWITCHING CHARACTERISTICS (Note 5) (C
= 50 pF, T
L
Characteristic
ООООООООООООО
Output Rise and Fall Time
, T
T
TLH
T
ООООООООООООО
TLH
T
TLH
= (1.5 ns/pF) CL + 25 ns
THL
, T
= (0.75 ns/pF) CL + 12.5 ns
THL
, T
= (0.55 ns/pF) CL + 9.5 ns
THL
Propagation Delay Time
ООООООООООООО
Clock to Q1
, t
t
PHL
ООООООООООООО
t
PHL
t
ООООООООООООО
PHL
= (1.7 ns/pF) CL + 315 ns
PLH
, t
= (0.66 ns/pF) CL + 137 ns
PLH
, t
= (0.5 ns/pF) CL + 95 ns
PLH
= 25C)
A
Symbol
ÎÎÎ
t
,
TLH
t
THL
ÎÎÎ
t
,
PLH
ÎÎÎ
t
PHL
ÎÎÎ
ÎÎÎ
V
DD
Vdc
ÎÎ
5.0
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
ÎÎ
15
Min
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
ÎÎ
−
ÎÎ
−
Typ
(Note 6)
ÎÎ
100
50
ÎÎ
40
ÎÎ
260
ÎÎ
115
ÎÎ
80
Max
ÎÎ
200
100
ÎÎ
80
ÎÎ
520
ÎÎ
230
ÎÎ
160
Clock to Q12
t
, t
PHL
ООООООООООООО
t
PHL
t
ООООООООООООО
PHL
= (1.7 ns/pF) CL + 2415 ns
PLH
, t
= (0.66 ns/pF) CL + 867 ns
PLH
, t
= (0.5 ns/pF) CL + 475 ns
PLH
Propagation Delay Time
Reset to Q
ООООООООООООО
ООООООООООООО
n
t
= (1.7 ns/pF) CL + 485 ns
PHL
t
= (0.86 ns/pF) CL + 182 ns
PHL
t
= (0.5 ns/pF) CL + 145 ns
PHL
Clock Pulse Width
ООООООООООООО
Clock Pulse Frequency
ООООООООООООО
ООООООООООООО
Clock Rise and Fall Time
ООООООООООООО
Reset Pulse Width
ООООООООООООО
Reset Removal Time
ООООООООООООО
ÎÎÎ
ÎÎÎ
t
PHL
ÎÎÎ
ÎÎÎ
t
WH
ÎÎÎ
f
cl
ÎÎÎ
ÎÎÎ
t
, t
TLH
THL
ÎÎÎ
t
WH
ÎÎÎ
t
rem
ÎÎÎ
5.0
ÎÎ
10
15
ÎÎ
ÎÎ
5.0
10
ÎÎ
15
5.0
10
ÎÎ
15
5.0
ÎÎ
10
15
ÎÎ
5.0
10
15
ÎÎ
5.0
10
ÎÎ
15
5.0
10
ÎÎ
15
−
ÎÎ
−
−
ÎÎ
ÎÎ
−
−
ÎÎ
−
385
150
ÎÎ
115
−
ÎÎ
−
−
ÎÎ
1625
ÎÎ
720
500
ÎÎ
ÎÎ
370
155
ÎÎ
115
140
55
ÎÎ
38
2.1
ÎÎ
7.0
10.0
ÎÎ
3250
ÎÎ
1440
1000
ÎÎ
ÎÎ
740
310
ÎÎ
230
−
−
ÎÎ
−
1.5
ÎÎ
3.5
4.5
ÎÎ
No Limit
ОООООООО
960
360
ÎÎ
270
130
50
ÎÎ
30
320
120
ÎÎ
80
65
25
ÎÎ
15
−
−
ÎÎ
−
−
−
ÎÎ
−
5. The formulas given are for the typical characteristics only at 25C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
Î
ns
Î
Î
ns
Î
Î
ns
Î
Î
ns
Î
Î
ns
Î
MHz
Î
Î
ns
Î
ns
Î
ns
Î
V
DD
500 F
PULSE
GENERATOR
I
D
Q1
C
Q2
Q
n
R
V
SS
20 ns20 ns
CLOCK
90%
50%
10%
50% DUTY CYCLE
Figure 1. Power Dissipation Test Circuit
and Waveform
0.01 F
CERAMIC
C
C
L
V
DD
PULSE
GENERATOR
C
L
Q1
C
Q2
Q
n
R
C
V
SS
L
C
L
C
L
L
CLOCK
V
DD
V
SS
20 ns20 ns
t
PLH
Q
90%
50%
10%
t
TLHtTHL
90%
50%
t
WH
10%
t
PHL
Figure 2. Switching Time Test Circuit
and Waveforms
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4
Page 5
MC14040B
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
1248163264128256512102420484096
Figure 3. Timing Diagram
APPLICATIONS INFORMATION
TIME−BASE GENERATOR
A 60 Hz sinewave obtained through a 1.0 Megohm
resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting
V
CC
1/6 of HC14A
Figure 4. Time−Base Generator
120Vac
60Hz
NOTE: Ground MUST be isolated
by a transformer or
opto−isolator for safety
reasons.
1.0M
≥20pF
outputs Q5, Q10, Q11, and Q12 division by 3600 is
accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.
V
CC
MC14040B
ClockQ5
Q10
Q11
Q12
13
12
10
9
1/2
14012B
1
2
8
4
5
1/2
14012B
1.0 Pulse/Minute
6
Output
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5
Page 6
MC14040B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
−A−
916
B
18
F
C
S
SEATING
−T−
PLANE
H
G
D
16 PL
0.25 (0.010)T
K
M
A
L
J
M
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MINMAXMINMAX
A 0.740 0.770 18.80 19.55
B 0.250 0.2706.356.85
C 0.145 0.1753.694.44
D 0.015 0.0210.390.53
F 0.0400.701.021.77
M
G0.100 BSC2.54 BSC
H0.050 BSC1.27 BSC
J 0.008 0.0150.210.38
K 0.110 0.1302.803.30
L 0.295 0.3057.507.74
M0 10 0 10
S 0.020 0.0400.511.01
MILLIMETERSINCHES
−T−
−A−
169
−B−
18
G
K
C
SEATING
PLANE
D
16 PL
0.25 (0.010)A
M
S
B
T
S
8 PLP
0.25 (0.010)B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
X 45
R
F
J
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MINMAXMINMAX
−−−2.05−−− 0.081
A
A
0.050.20 0.002 0.008
1
0.350.50 0.014 0.020
b
0.180.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.105.45 0.201 0.215
E
1.27 BSC0.050 BSC
e
H
7.408.20 0.291 0.323
E
0.500.85 0.020 0.033
L
L
1.101.50 0.043 0.059
E
0
M
Q
0.700.90 0.028 0.035
1
−−−0.78−−− 0.031
Z
INCHES
10
10
0
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MC14040B/D
8
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