Datasheet MC14035BCL, MC14035BCP, MC14035BD Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATAMC14035B

144

   

The MC14035B 4–bit shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of a 4–stage clocked serial–shift register with synchronous parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input allows serial–right shifting of data or synchronous parallel loading via inputs DP0 thru DP3. The True/Complement (T/C) input determines whether the outputs display the Q or Q

outputs of the flip–flop stages. J–K logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial “D” input.

This device may be effectively used for shift–right/shift–left registers, parallel–to–serial/serial–to–parallel conversion, sequence generation, up/ down Johnson or ring counters, pseudo–random code generation, frequency and phase comparators, sample and hold registers, etc . . .

• 4–Stage Clocked Serial–Shift Operation

• Synchronous Parallel Loading of all Four Stages

• J–K Serial Inputs on First Stage

• Asynchronous True/Complement Control of all Outputs

• Fully Static Operation

• Asynchronous Master Reset

• Data Transfer Occurs on the Positive–Going Clock Transition

• No Limit on Clock Rise and Fall Times

• All Inputs are Buffered

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

lin, l

out

Input or Output Current (DC or Transient), per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE

Inputs

t

Output

C J K R

tn Output

Q

0

0 0 0 0 0 1 0 Q0 (n – 1) 1 0 0 Q0 (n – 1)

1 1 0 1 X X 0 Q0 (n – 1)

X X X 1 0

X = Don’t Care P/S = 0 = Serial Mode T/C = 1 = True Outputs



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D

P3

Q3

Q2

Q1

V

DD

D

P0

D

P1

D

P2

J

K

T/C

Q0

V

SS

P/S

C

R

MOTOROLA CMOS LOGIC DATA

145

MC14035B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

V

IL

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

V

IH

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

I

OH

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2

– 0.88

– 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

I

OL

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

5.0

7.5

—

ÎÎÎ

—

pF

Quiescent Current

(Per Package)

I

DD

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs all buffers switching)

I

T

5.0 10 15

IT = (1.0 µA/kHz) f + I

DD

IT = (2.0 µA/kHz) f + I

DD

IT = (3.0 µA/kHz) f + I

DD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATAMC14035B

146

SWITCHING CHARACTERISTICS (C

L

= 50 pF, TA = 25_C, See Figure 1)

Characteristic

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

T

TLH

, T

THL

= (1.5 ns/pF) CL + 25 ns

T

TLH

, T

THL

= (0.75 ns/pF) CL + 12.5 ns

T

TLH

, T

THL

= (0.55 ns/pF) CL + 12.5 ns

ÎÎÎÎ

t

TLH

,

t

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

80

ns

Propagation Delay Time, Clock or Reset to Q

T

PLH

, T

PHL

= (1.75 ns/pF) CL + 223 ns

T

PLH

, T

PHL

= (0.70 ns/pF) CL + 89 ns

T

PLH

, T

PHL

= (0.53 ns/pF) CL + 67 ns

ÎÎÎÎ

t

PLH

,

t

PHL

5.0 10 15

ÎÎÎÎ

— — —

300 130

95

600 260 190

ns

Clock Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

335 165 125

135

45 40

— — —

ns

Reset Pulse Width

ÎÎÎÎ

t

WH

5.0 10 15

ÎÎÎÎ

400 175 130

80 40 35

— — —

ns

Reset Removal Time

ÎÎÎÎ

t

rem

5.0 10 15

ÎÎÎÎ

80 30 25

40 15 10

— — —

ns

Clock Pulse Rise and Fall Time

ÎÎÎÎ

t

TLH

, t

THL

5.0 10 15

ОООООООООО

No Limit

—

Clock Pulse Frequency

ÎÎÎÎ

f

cl

5.0 10 15

ÎÎÎÎ

— — —

2.5

6.0 10

1.2

2.0

3.0

MHz

J–K to Clock Setup Time

ÎÎÎÎ

t

su

5.0 10 15

ÎÎÎÎ

500 200 150

120

50 30

— — —

ns

Clock to J–K Hold Time

ÎÎÎÎ

t

h

5.0 10 15

ÎÎÎÎ

40 30 25

– 40

– 5

0

— — —

ns

P/S to Clock Setup Time

ÎÎÎÎ

t

su

5.0 10 15

ÎÎÎÎ

500 200 150

25 10

7.5

— — —

ns

Clock to P/S Hold Time

ÎÎÎÎ

t

h

5.0 10 15

ÎÎÎÎ

30 20 20

– 70 – 20 – 10

— — —

ns

DP to Clock Setup Time

ÎÎÎÎ

t

su

5.0 10 15

ÎÎÎÎ

500 200 150

90 20 15

— — —

ns

Clock to DP Hold Time

ÎÎÎÎ

t

h

5.0 10 15

ÎÎÎÎ

90 40 40

– 25

0 5

— — —

ns

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Timing Diagram

RESET

50%

t

rem CLOCK INPUT

J–K INPUT

P/S INPUT

D

P0

INPUT

Q

0

T/C INPUT LOW

50%

t

WH

1/f

cl

t

h

t

su

t

su

t

su

t

h

t

THL

t

TLH

t

h

t

su

90%

10%

50%

t

PHL

t

PLH

t

PHL

t

PLH

50%

MOTOROLA CMOS LOGIC DATA

147

MC14035B

LOGIC DIAGRAM

DP312 DP211 DP110 DP09 P/S 7 J 4

K

3

C 6

R 5

T/C 2

13

14

15

1

Q3

Q2

Q1

Q0

D Q

R

C

D Q

R

C

D Q

R

C

D Q

R

C

APPLICATION DIAGRAM

Shift Left/Shift Right Register

LEFT SHIFT SERIAL INPUT

RIGHT SHIFT SERIAL INPUT

RESET

CLOCK LEFT/RIGHT SHIFT SELECT

LEFT SHIFT SERIAL OUTPUT

RIGHT SHIFT SERIAL OUTPUT

Q0 Q1 Q2

Q3

V

DD

V

DD

16

V

DD

15Q114Q213Q312

D

P3

11

D

P2

10

D

P1

9

D

P0

Q01T/C2K

3J4R5C6

P/S7V

SS 8

MOTOROLA CMOS LOGIC DATAMC14035B

148

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

149

MC14035B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

_ _ _ _

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MC14035B/D

*MC14035B/D*

◊

Datasheet MC14035BCL, MC14035BCP, MC14035BD Datasheet (Motorola)

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