Datasheet MC14029BD, MC14029BDR2, MC14029BF, MC14029BFEL, MC14029BCP Datasheet (MOTOROLA)

MC14029B

Binary/Decade Up/Down Counter

The MC14029B Binary/Decade up/down counter is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide toggle flip–flop capability. The counter can be used in either Binary or BCD operation. This complementary MOS counter finds primary use in up/down and difference counting and frequency synthesizer applications where low power dissipation and/or high noise immunity is desired. It is also useful in A/D and D/A conversion and for magnitude and sign generation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going

Edge of Clock

• Asynchronous Preset Enable Operation

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

• Pin for Pin Replacement for CD4029B

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

DD

Vin, V

Iin, I

P

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

D

A

L

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation,

per Package (Note 3.) Ambient Temperature Range –55 to +125 °C Storage Temperature Range –65 to +150 °C Lead Temperature

(8–Second Soldering)

v (Vin or V

SS

or VDD). Unused outputs must be left open.

SS

) v VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14029BCP

AWLYYWW

1

16

14029B

AWLYWW

1

16

MC14029B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14029BCP PDIP–16 2000/Box MC14029BD SOIC–16 2400/Box MC14029BDR2 SOIC–16 2500/Tape & Reel MC14029BF SOEIAJ–16 See Note 1. MC14029BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14029B/D

MC14029B

V

DD

Î

PIN ASSIGNMENT

TRUTH TABLE

Preset

Carry In Up/Down

Enable

Action

1 X 0 No Count 0 1 0 Count Up 0 0 0 Count Down X X 1 Preset

X = Don’t Care

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

– 55_C

Min

— —

Î

—

4.95

Î

9.95

14.95

Î

—

Î

— —

Î

3.5

Î

7.0 11

Î

– 3.0

Î

– 0.64

– 1.6

Î

– 4.2

0.64

Î

1.6

4.2

Î

— —

—

Î

— —

Î

ООООООООООООООО

Characteristic

Output Voltage “0” Level

= VDD or 0

V

ОООООООО

in

ОООООООО

V

= 0 or V

in

ОООООООО

DD

“1” Level

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

ОООООООО

= 9.0 or 1.0 Vdc)

(V

O

(V

= 13.5 or 1.5 Vdc)

O

ОООООООО

“1” Level

= 0.5 or 4.5 Vdc)

(V

O

ОООООООО

(V

= 1.0 or 9.0 Vdc)

O

(V

= 1.5 or 13.5 Vdc)

O

ОООООООО

Output Drive Current

(V

= 2.5 Vdc) Source

OH

ОООООООО

= 4.6 Vdc)

(V

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

(V

= 0)

in

Quiescent Current

ОООООООО

(Per Package)

ОООООООО

Total Supply Current

(Dynamic plus Quiescent,

ОООООООО

Per Package)

= 50 pF on all outputs, all

(C

L

ОООООООО

buffers switching)

(5.) (6.)

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

IL

ÎÎ

V

IH

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

in

I

DD

ÎÎ

I

T

ÎÎ

V Vdc

5.0 10

Î

15

5.0

Î

10 15

Î

5.0

Î

10 15

Î

5.0

Î

10 15

Î

5.0

Î

5.0 10

Î

15

5.0

Î

10 15

Î

15 —

5.0

Î

10 15

Î

5.0 10

Î

15

Î

SS

)

Max

0.05

Î

0.05

Î

1.5

Î

3.0

4.0

Î

± 0.1

5.0

Î

— — —

— — — —

— — —

—

10 20

25_C

Min

— —

ÎÎ

—

4.95

ÎÎ

9.95

14.95

ÎÎ

—

ÎÎ

— —

ÎÎ

3.5

ÎÎ

7.0 11

ÎÎ

– 2.4

ÎÎ

– 0.51

– 1.3

ÎÎ

– 3.4

0.51

ÎÎ

1.3

3.4

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

(4.)

Typ

0 0

Î

0

5.0

Î

10 15

Î

2.25

Î

4.50

6.75

Î

2.75

Î

5.50

8.25

Î

– 4.2

Î

– 0.88 – 2.25

Î

– 8.8

0.88

Î

2.25

8.8

Î

±0.00001

5.0

0.005

Î

0.010

0.015

Î

IT = (0.58 µA/kHz) f + I IT = (1.20 µA/kHz) f + I IT = (1.70 µA/kHz) f + I

PE Q3

P3 P0

C

in

Q0

C

out

V

SS

ÎÎ

1 2 3 4

6 7 8

Max

0.05

0.05 —

— —

1.5

3.0

4.0

— — —

— — — —

— — —

± 0.1

7.5

5.0 10 20

DD DD DD

16 15 14 13 125 11 10

9

Min

— —

Î

—

4.95

Î

9.95

14.95

Î

—

Î

— —

Î

3.5

Î

7.0 11

Î

– 1.7

Î

– 0.36

– 0.9

Î

– 2.4

0.36

Î

0.9

2.4

Î

— —

—

Î

— —

Î

V

DD

CLK Q2 P2

P1 Q1 U/D B/D

125_C

Max

0.05

Î

0.05

Î

± 1.0

Î

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

T

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

150 300 600

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

µAdc

Î

µAdc

Î

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2

MC14029B

Î

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

= 25_C)

A

All Types

Characteristic

Output Rise and Fall Time

t

, t

TLH

ООООООООООООО

t

TLH

t

ООООООООООООО

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time

Clk to Q

ООООООООООООО

Clock Pulse Width

ООООООООООООО

t

PLH

t

PLH

t

PLH

Clk to C

t

PLH

t

PLH

t

PLH

Cin to C

t

PLH

t

PLH

t

PLH

PE to Q

t

PLH

t

PLH

t

PLH

PE to C

t

PLH

t

PLH

t

PLH

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1.7 ns/pF) CL + 95 ns

PHL

, t

= (0.66 ns/pF) CL + 47 ns

PHL

, t

= (0.5 ns/pF) CL + 35 ns

PHL

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1. 7 ns/pF) CL + 465 ns

PHL

, t

= (0.66 ns/pF) CL + 192 ns

PHL

, t

= (0.5 ns/pF) CL + 125 ns

PHL

Clock Pulse Frequency

ООООООООООООО

Preset Removal Time The Preset Signal must be low prior to a positive–going

ООООООООООООО

transition of the clock. Clock Rise and Fall Time

ООООООООООООО

Carry In Setup Time

ООООООООООООО

Up/Down Setup Time

ООООООООООООО

Binary/Decade Setup Time

ООООООООООООО

Preset Enable Pulse Width

ООООООООООООО

Symbol

t

,

TLH

t

THL

ÎÎÎ

t

,

PLH

t

PHL

ÎÎÎ

t

,

PLH

ÎÎÎ

t

PHL

ÎÎÎ

V

DD

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

t

,

PLH

ÎÎÎ

t

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

15

t

,

PLH

ÎÎÎ

t

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

15

t

,

PLH

ÎÎÎ

t

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

15

t

W(cl)

ÎÎÎ

f

cl

ÎÎÎ

t

rem

ÎÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

t

r(cl)

ÎÎÎ

t

f(cl)

ÎÎÎ

t

su

ÎÎÎ

5.0

ÎÎ

10

1 5

ÎÎ

5.0 10

ÎÎ

15

5.0

ÎÎÎÎÎÎ

ÎÎÎ

t

W

10 15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎÎ

ÎÎ

15

Min

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

180

ÎÎ

80 60

ÎÎ

— —

ÎÎ

—

160

80

ÎÎ

60 —

ÎÎ

— —

ÎÎ

150

60

ÎÎ

40

340 140

ÎÎ

100 320

ÎÎ

140 100

ÎÎ

130

70

ÎÎ

50

(8.)

Typ

100

ÎÎ

50 40

ÎÎ

200 100

ÎÎ

90

ÎÎ

250 130

ÎÎ

85

ÎÎ

175

50

ÎÎ

50

ÎÎ

235 100

ÎÎ

80

ÎÎ

320 145

ÎÎ

105

90

ÎÎ

40 30

ÎÎ

4.0

8.0

ÎÎ

10 80

40

ÎÎ

30 —

ÎÎ

— —

ÎÎ

75 30

ÎÎ

20

170

70

ÎÎ

50

160

ÎÎ

70 50

ÎÎ

65 35

ÎÎ

25

Max

200

ÎÎ

100

80

ÎÎ

400 200

ÎÎ

180

ÎÎ

500 260

ÎÎ

190

ÎÎ

360 120

ÎÎ

100

ÎÎ

470 200

ÎÎ

160

ÎÎ

640 290

ÎÎ

210

—

ÎÎ

— —

ÎÎ

2.0

4.0

ÎÎ

5.0 —

—

ÎÎ

— 15

ÎÎ

5 4

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

— —

ÎÎ

—

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

MHz

Î

ns

Î

µs

Î

ns

Î

ns

Î

ns

Î

ns

Î

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3

PULSE

GENERATOR

500 pF

MC14029B

V

DD

I

D

PE

Q0

C

in

Q1

B/D U/D

Q2

CLK P0 P1

Q3 P2 P3 C

out

0.01 µF CERAMIC

C

L

C

L

C

L

C

L

PROGRAMMABLE

CARRY IN

OR

UP/DOWN

OR BINARY/DECADE

CLOCK

PRESET ENABLE

Q0 OR CARRY OUT

20 ns 20 ns

90%

CLK

50%

VARIABLE

10%

V

DD

V

SS

WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

V

DD

PULSE

GENERATOR

t

su

50%

t

THL

90%

10%

50%

PE C B/D U/D CLK

P0 P1 P2 P3 C

t

W

t

rem

t

W

C

ONLY

out

t

PHL

Q0

in

Q1 Q2

Q3

out

V

SS

1/f

cl

10%

t

PLH

C

20 ns

L

t

90%

t

TLH

PLH

C

L

C

L

C

L

C

L

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

Figure 2. Switching Time Test Circuit and Waveforms

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4

CLOCK

IN

CARRY

UP/DOWN

BINARY/DECADE

PE

P0 P1

P2 P3

Q0 Q1 Q2 Q3

OUT

CARRY

COUNT

MC14029B

TIMING DIAGRAM

012345678987654321009670

INPUT

CLOCK

Q3 Q2 Q1 Q0

C

out

MC14029B

U/D B/D

MSD

P3 P2 P1 P0 CLK

V

“1” “2” “3”

CLOCK

(LSD)

C

out 1

C

out 2

C

(MSD)

out 3

PE

COUNT

DD

123

C PE

122

Q3 Q2 Q1 Q0

C

in

U/D

out

MC14029B

B/D

C PE

in

P3 P2 P1 P0 CLK

V

DD

121

120

119

101

100

99

11

10

9

Q3 Q2 Q1 Q0

C

out

MC14029B

U/D B/D

LSD

P3 P2 P1 P0 CLK

V

DD

1

0

123

C

in

PE

DD

OUTPUT

122

*tW ^ 900 ns @ VDD = 5 V

Figure 3. Divide by N BCD Down Counter and Timing Diagram

(Shown for N = 123)

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5

MC14029B

LOGIC DIAGRAM

7

CARRY OUT

P3

PE

P2

PE

P1

PE

Q3

Q2

Q1

TE

Q3 CLK

Q2 CLK

Q1 CLK

2Q3

14 Q21Q16Q0

4P0 12P1 13P2 3P3

9

BINARY/DECADE

1

PRESET ENABLE

P0

Q0

PE

TE

CLK

5

CARRY IN

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6

10

UP/DOWN

15

CLOCK

–T–

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14029B

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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7

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14029B

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy, England, Ireland

CENTRAL/SOUTH AMERICA:

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–asia@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: 81–3–5740–2745 Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local Sales Representative.

http://onsemi.com

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