Datasheet MC14028BFEL, MC14028BFL1, MC14028BCP, MC14028BD, MC14028BDR2 Datasheet (MOTOROLA)
...Page 1
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14028B/D
MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (one–of–ten) decoded output,
while a 3–bit binary input provides a decoded octal (one–of–eight)
code output with D forced to a logic “0”. Expanded decoding such as
binary–to–hexadecimal (one–of–16), etc., can be achieved by using
other MC14028B devices. The part is useful for code conversion,
address decoding, memory selection control, demultiplexing, or
readout decoding.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Positive Logic Design
• Low Outputs on All Illegal Input Combinations
• Similar to CD4028B.
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
Vin, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or VDD). Unused outputs must be left open.
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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14028BCP PDIP–16 2000/Box
MC14028BD SOIC–16 2400/Box
MC14028BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14028BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14028B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14028B
AWLYWW
MC14028BF SOEIAJ–16 See Note 1.
MC14028BFEL SOEIAJ–16 See Note 1.
Page 2
MC14028B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
C
B
Q1
Q3
V
DD
Q8
A
D
Q7
Q0
Q2
Q4
V
SS
Q6
Q5
Q9
TRUTH TABLE
DC B A Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0
00000000000001
00010000000010
00100000000100
00110000001000
01000000010000
01010000100000
01100001000000
01110010000000
10000100000000
10011000000000
10100000000000
10110000000000
11000000000000
11010000000000
11100000000000
11110000000000
BLOCK DIAGRAM
8421
BCD
INPUTS
DECIMAL
DECODED
OUTPUTS
OCTAL
DECODED
OUTPUTS
3
14
2
15
1
6
7
4
9
5
A
B
C
DQ9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
3–BIT
BINARY
INPUTS
10
13
12
11
V
DD
= PIN 16
V
SS
= PIN 8
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
ОООООООО
Î
Output Voltage “0” Level
V
in
= VDD or 0
ÎÎ
Î
V
OL
Î
Î
5.0
10
15
Î
Î
—
—
—
Î
Î
0.05
0.05
0.05
ÎÎ
Î
—
—
—
Î
Î
0
0
0
ÎÎ
Î
0.05
0.05
0.05
Î
Î
—
—
—
Î
Î
0.05
0.05
0.05
Î
Î
Vdc
ОООООООО
Î
“1” Level
V
in
= 0 or V
DD
ÎÎ
Î
V
OH
Î
Î
5.0
10
15
Î
Î
4.95
9.95
14.95
Î
Î
—
—
—
ÎÎ
Î
4.95
9.95
14.95
Î
Î
5.0
10
15
ÎÎ
Î
—
—
—
Î
Î
4.95
9.95
14.95
Î
Î
—
—
—
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
ÎÎ
Î
ÎÎ
Î
V
IL
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
1.5
3.0
4.0
ÎÎ
Î
ÎÎ
Î
—
—
—
Î
Î
Î
Î
2.25
4.50
6.75
ÎÎ
Î
ÎÎ
Î
1.5
3.0
4.0
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
1.5
3.0
4.0
Î
Î
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
ÎÎ
Î
ÎÎ
Î
V
IH
Î
Î
Î
Î
5.0
10
15
Î
Î
Î
Î
3.5
7.0
11
Î
Î
Î
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
3.5
7.0
11
Î
Î
Î
Î
2.75
5.50
8.25
ÎÎ
Î
ÎÎ
Î
—
—
—
Î
Î
Î
Î
3.5
7.0
11
Î
Î
Î
Î
—
—
—
Î
Î
Î
Î
Vdc
ОООООООО
Î
ОООООООО
Î
ОООООООО
Î
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
I
OH
Î
Î
Î
Î
Î
Î
5.0
5.0
10
15
Î
Î
Î
Î
Î
Î
– 3.0
– 0.64
– 1.6
– 4.2
Î
Î
Î
Î
Î
Î
—
—
—
—
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
– 2.4
– 0.51
– 1.3
– 3.4
Î
Î
Î
Î
Î
Î
– 4.2
– 0.88
– 2.25
– 8.8
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
—
—
—
—
Î
Î
Î
Î
Î
Î
– 1.7
– 0.36
– 0.9
– 2.4
Î
Î
Î
Î
Î
Î
—
—
—
—
Î
Î
Î
Î
Î
Î
mAdc
ОООООООО
Î
(VOL = 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
ÎÎ
Î
I
OL
Î
Î
5.0
10
15
Î
Î
0.64
1.6
4.2
Î
Î
—
—
—
ÎÎ
Î
0.51
1.3
3.4
Î
Î
0.88
2.25
8.8
ÎÎ
Î
—
—
—
Î
Î
0.36
0.9
2.4
Î
Î
—
—
—
Î
Î
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
µAdc
ОООООООО
Î
Input Capacitance
(V
in
= 0)
ÎÎ
Î
C
in
Î
Î
—
Î
Î
—
Î
Î
—
ÎÎ
Î
—
Î
Î
5.0
ÎÎ
Î
7.5
Î
Î
—
Î
Î
—
Î
Î
pF
ОООООООО
Î
Quiescent Current
(Per Package)
ÎÎ
Î
I
DD
Î
Î
5.0
10
15
Î
Î
—
—
—
Î
Î
5.0
10
20
ÎÎ
Î
—
—
—
Î
Î
0.005
0.010
0.015
ÎÎ
Î
5.0
10
20
Î
Î
—
—
—
Î
Î
150
300
600
Î
Î
µAdc
ОООООООО
Î
ОООООООО
Î
ОООООООО
Î
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
I
T
Î
Î
Î
Î
Î
Î
5.0
10
15
ООООООООООООООО
Î
ООООООООООООООО
Î
ООООООООООООООО
Î
IT = (0.3 µA/kHz) f + I
DD
IT = (0.6 µA/kHz) f + I
DD
IT = (0.9 µA/kHz) f + I
DD
Î
Î
Î
Î
Î
Î
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
I
T(CL
) = IT(50 pF) + (CL – 50) Vfk
where: I
T
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
V
DD
Min
Typ
(8.)
Max
Unit
ООООООООООООО
Î
ООООООООООООО
Î
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
ÎÎÎ
Î
ÎÎÎ
Î
t
TLH
,
t
THL
ÎÎ
Î
ÎÎ
Î
5.0
10
15
ÎÎ
Î
ÎÎ
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
100
50
40
ÎÎ
Î
ÎÎ
Î
200
100
80
Î
Î
Î
Î
ns
ООООООООООООО
Î
ООООООООООООО
Î
Propagation Delay Time
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 65 ns
ÎÎÎ
Î
ÎÎÎ
Î
t
PLH
,
t
PHL
ÎÎ
Î
ÎÎ
Î
5.0
10
15
ÎÎ
Î
ÎÎ
Î
—
—
—
ÎÎ
Î
ÎÎ
Î
300
130
90
ÎÎ
Î
ÎÎ
Î
600
260
180
Î
Î
Î
Î
ns
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 4
MC14028B
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4
Figure 1. Dynamic Signal Waveforms
Inputs B, C, and D
switching in respect
to a BCD code.
Inputs A, B, and D low.
All outputs connected
to respective C
L
loads.
f in respect to a system
clock.
20 ns 20 ns
90%
50%
10%
1/f
V
DD
V
SS
20 ns 20 ns
INPUT A
INPUT C
Q4
10%
90%
50%
V
DD
V
SS
V
OH
V
OL
t
PLH
t
PHL
t
TLH
t
THL
50%
90%
10%
LOGIC DIAGRAM
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D
C
B
A
Page 5
MC14028B
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5
APPLICATIONS INFORMATION
Expanded decoding can be performed by using the
MC14028B and other CMOS Integrated Circuits. The
circuit in Figure 2 converts any 4–bit code to a decimal or
hexadecimal code. The accompanying table shows the input
binary combinations, the associated “output numbers” that
go “high” when selected, and the “redefined output
numbers” needed for the proper code. For example: For the
combination DCBA = 011 1 the output number 7 is redefined
for the 4–bit binary, 4–bit gray, excess–3, or excess–3 gray
codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6–bit
binary 1–of–64 decoder using nine MC14028B circuits and
two MC14069UB inverters.
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
Figure 2. Code Conversion Circuit and Truth Table
INPUTS
D
MC14028B
CBA
DCBA DCBA
MC14028B
Q9 Q0 Q9 Q0
15 –8 15 –0
OUTPUT NUMBERS
Code and Redefined
Output Numbers
Hexadecimal Decimal
Inputs Output Numbers
D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 2
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2 0 3 3
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7 1 4 4
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6 2 3
0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4 3 1 4
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5 4 2
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 5
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6 5
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9 6
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8 5
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 6
1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9 6 7 7
1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11 8 8 8
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10 7 9 9
4–Bit
Binary
4–Bit
Gray
Excess–3
Excess–3
Gray
Aiken
4221
Page 6
MC14028B
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6
Figure 3. Six–Bit Binary 1–of–64 Decoder
INPUTS
A B C D E F INHIBIT
(NO SELECTION)
AB C –D
Q0 Q9
MC14028B
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
ABCD
MC14028B
Q0 Q9
70 8 15 16 23 24 31 32 39 40 47 48 55 56 63
*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)
Figure 4. Decimal Digit Display Application
A
Q9
MC14028B
B
C
D
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
9
0
2910
APPROPRIATE
VOLTAGE
NEON
DISPLAY
APPROPRIATE
VOLTAGE
INCANDESCENT
DISPLAY
OR
Page 7
MC14028B
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7
P ACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
Page 8
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8
P ACKAGE DIMENSIONS
H
E
A
1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .
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MC14028B/D
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