Datasheet MC14027BFR1, MC14027BFL1, MC14027BFL2, MC14027BCP, MC14027BD Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14027B/D

MC14027B

Dual J-K Flip-Flop

The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Swing Independent of Fanout

• Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4027B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14027BCP PDIP–16 2000/Box
MC14027BD SOIC–16 2400/Box
MC14027BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14027BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14027B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14027B

AWLYWW

MC14027BF SOEIAJ–16 See Note 1.
MC14027BFEL SOEIAJ–16 See Note 1.

MC14027B

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2

TRUTH TABLE

Inputs Outputs*

C

†

J K S R Q

n

‡

Q

n+1

Q

n+1

1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
1 1 0 0 Qo Qo Qo
X X 0 0 X Q

n

Q

n

X X X 1 0 X 1 0
X X X 0 1 X 0 1
X X X 1 1 X 1 1

X = Don’t Care

‡

= Present State

†

= Level Change * = Next State

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

R

B

C

B

Q

B

Q

B

V

DD

S

B

J

B

K

B

R

A

C

A

Q

A

Q

A

V

SS

S

A

J

A

K

A

PIN ASSIGNMENT

BLOCK DIAGRAM

12

11

13

10

9

4

5

3

6

7

14

15

2

1

S

S

R

R

K

C

J

K

C

JQ

Q

Q

Q

VDD = PIN 16

V

SS

= PIN 8

No
Change

MC14027B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

Vin = 0 or V

DD

“1” Level

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

(VO = 0.5 or 4.5 Vdc) “1” Level
(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

– 4.2
– 0.88
– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

mAdc

ОООООООО

Î

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

0.64

1.6

4.2

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

0.51

1.3

3.4

Î

Î

Î

Î

0.88

2.25

8.8

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.36

0.9

2.4

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

(V

in

= 0)

C

in

—

—

—

—

5.0

7.5

—

—

pF

ОООООООО

Î

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

ÎÎ

Î

I

DD

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.0

2.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.002

0.004

0.006

ÎÎ

Î

ÎÎ

Î

1.0

2.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

30
60

120

Î

Î

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.8 µA/kHz) f + I

DD

IT = (1.6 µA/kHz) f + I

DD

IT = (2.4 µA/kHz) f + I

DD

Î

Î

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14027B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 12.5 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Times**

Clock to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 90 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 42 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 25 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

175

75
50

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

350
150
100

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Set to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 90 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 42 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 25 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

175

75
50

ÎÎ

Î

ÎÎ

Î

350
150
100

Î

Î

Î

Î

ООООООООООООО

Î

ООООООООООООО

Î

Reset to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 265 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 67 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 50 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

350
100

75

ÎÎ

Î

ÎÎ

Î

450
200
150

Î

Î

Î

Î

ООООООООООООО

Î

Setup Times

ÎÎÎ

Î

t

su

ÎÎ

Î

5.0
10
15

ÎÎ

Î

140

50
35

ÎÎ

Î

70
25
17

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Hold Times

ÎÎÎ

Î

t

h

ÎÎ

Î

5.0
10
15

ÎÎ

Î

140

50
35

ÎÎ

Î

70
25
17

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Clock Pulse Width

ÎÎÎ

Î

ÎÎÎ

Î

tWH, t

WL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

330
110

75

ÎÎ

Î

ÎÎ

Î

165

55
38

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Frequency

ÎÎÎ

Î

f

cl

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

3.0

9.0
13

ÎÎ

Î

1.5

4.5

6.5

Î

Î

MHz

ООООООООООООО

Î

Clock Pulse Rise and Fall Time

ÎÎÎ

Î

t

TLH

, t

THL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

—
—
—

ÎÎ

Î

15

5.0

4.0

Î

Î

µs

ООООООООООООО

Î

ООООООООООООО

Î

Removal Times

Set

ÎÎÎ

Î

ÎÎÎ

Î

t

rem

ÎÎ

Î

ÎÎ

Î

5
10
15

ÎÎ

Î

ÎÎ

Î

90
45
35

ÎÎ

Î

ÎÎ

Î

10

5
3

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Reset

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5
10
15

ÎÎ

Î

ÎÎ

Î

50
25
20

ÎÎ

Î

ÎÎ

Î

– 30
– 15
– 10

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ООООООООООООО

Î

Set and Reset Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

250
100

70

ÎÎ

Î

125

50
35

ÎÎ

Î

—
—
—

Î

Î

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14027B

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5

Figure 1. Dynamic Signal Waveforms

(J, K, Clock, and Output)

Figure 2. Dynamic Signal Waveforms

(Set, Reset, Clock, and Output)

20 ns 20 ns

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

90%

50%

10%

20 ns 20 ns

t

su

90%

50%

10%

t

su

t

h

20 ns 20 ns

90%

50%

10%

t

WL

t

WH

1

f

cl

t

PLH

t

PHL

90%

50%
10%

t

TLH

t

THL

Q

C

K

J

Inputs R and S low.
For the measurement of t

WH

, I/fcl, and P

D

the Inputs J and K are kept high.

20 ns 20 ns

90%

50%

10%

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

t

rem

t

w

20 ns

20 ns

90%

50%

10%

t

w

t

PLH

t

PHL

50%

Q or Q

CLOCK

SET OR

RESET

LOGIC DIAGRAM

(1/2 of Device Shown)

S

J

K

R

CC

C

C

C

C

C

C

C

C

C

Q

Q

MC14027B

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6

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14027B

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7

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14027B

http://onsemi.com

8

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