Datasheet MC14024BFL1, MC14024BFL2, MC14024BFR1, MC14024BFR2, MC14024BF Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14024B/D

MC14024B

7-Stage Ripple Counter

The MC14024B is a 7–stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.

• Diode Protection on All Inputs

• Output Transitions Occur on the Falling Edge of the Clock Pulse

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4024B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note NO TAG)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note NO TAG)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14024BCP PDIP–14 2000/Box
MC14024BD SOIC–14

2750/Box
MC14024BDR2 SOIC–14 2500/Tape & Reel
MC14024BF SOEIAJ–14 See Note 1.

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14024BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

14024B

AWLYWW

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14024B

AWLYWW

MC14024BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

MC14024B

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2

TRUTH TABLE

Clock Reset State

0 0 No Change
0 1 All Outputs Low
1 0 No Change
1 1 All Outputs Low

0 No Change
1 All Outputs Low
0 Advance One Count
1 All Outputs Low

11

12

13

14

8

9

105

4

3

2

1

7

6

NC

Q2

Q1

NC

V

DD

NC

Q3

Q6

Q7

RESET

CLOCK

V

SS

Q4

Q5

PIN ASSIGNMENT

VDD = PIN 14

V

SS

= PIN 7

NC = NO CONNECTION

LOGIC DIAGRAM

CLOCK

RESET

2

1

12
Q1

11

Q2

4

Q6

3

Q7

Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5

CQ

RQ

CQ

RQ

CQ

RQ

CQ

RQ

MC14024B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

Vin = 0 or V

DD

“1” Level

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

(VO = 0.5 or 4.5 Vdc) “1” Level
(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

– 4.2
– 0.88
– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

mAdc

ОООООООО

Î

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

0.64

1.6

4.2

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

0.51

1.3

3.4

Î

Î

Î

Î

0.88

2.25

8.8

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.36

0.9

2.4

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

(V

in

= 0)

C

in

—

—

—

—

5.0

7.5

—

—

pF

ОООООООО

Î

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

ÎÎ

Î

I

DD

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

5.0
10
20

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.005

0.010

0.015

ÎÎ

Î

ÎÎ

Î

5.0
10
20

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

150
300
600

Î

Î

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.31 µA/kHz) f + I

DD

IT = (0.60 µA/kHz) f + I

DD

IT = (1.89 µA/kHz) f + I

DD

Î

Î

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14024B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time

Clock to Q1

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 295 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 117 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 85 ns

Clock to Q7

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 915 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 367 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 275 ns

Reset to Q

n

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 415 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 217 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 155 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

5.0
10
15

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

—
—
—

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

380
150
110

1000

400
300

500
250
180

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

600
230
175

2000

750
565

800
400
300

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

500
165
125

ÎÎ

Î

200

60
40

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Reset Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

600
350
260

ÎÎ

Î

375
200
150

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Reset Removal Time

ÎÎÎ

Î

ÎÎÎ

Î

t

rem

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

625
190
145

ÎÎ

Î

ÎÎ

Î

250

75
50

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Input Rise and Fall Time

ÎÎÎ

Î

t

TLH

, t

THL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

—
—
—

ÎÎ

Î

1.0

8.0

200

Î

Î

s
ms
µs

ООООООООООООО

Î

Input Pulse Frequency

ÎÎÎ

Î

f

cl

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

2.5

8.0
12

ÎÎ

Î

1.0

3.0

4.0

Î

Î

MHz

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14024B

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5

EXTERNAL

POWER

SUPPLY

EXTERNAL

POWER
SUPPLY

Figure 1. Typical Output Source

Characteristics Test Circuit

Figure 2. Typical Output Sink

Characteristics Test Circuit

V

DD

V

DD

V

SS

I

OH

VOL = V

out

CRQ

n

COUNT Qn TO A
LOGIC “1” LEVEL.

V

DD

VOH = V

out

V

SS

I

OL

CRQ

n

Figure 3. Power Dissipation Test Circuit

V

DD

500 µF

0.01 µF
CERAMIC

PULSE

GENERATOR

f

C

RQ7

Q6

Q5

Q4

Q3

Q2

Q1

V

SS

I

D

C

L

C

L

C

L

C

L

C

L

C

L

C

L

MC14024B

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6

Figure 4. Functional Waveforms

CLOCK (1)

RESET (2)

Q1 (12)

Q2 (11)

Q3 (9)

Q4 (6)

Q5 (5)

Q6 (4)

Q7 (3)

t

WL

t

WH

t

rem

t

PLH1

t

TLH

t

TLH

t

TLH

t

TLH

t

TLH

t

TLH

t

TLH

t

PHL1

t

PLH2

t

PHL2

t

PHL3

t

PHL4

t

PHL5

t

PHL6

t

PHL7

t

PLH3

t

PLH4

t

PLH5

t

PLH6

t

PLH7

50%

50%

50%

50%

50%

50%

50%

50%

90%

90%

10%

10%

10%

90%

t

THL

t

THL

t

THL

t

THL

t

THL

t

THL

t

THL

t

R1

t

R2

t

R3

t

R4

t

R5

t

R6

t

R7

V

DD

1 2 4 8 16 32 64 128 255

VSSVDDVSSV

OH

V

OH

V

OH

V

OH

V

OH

V

OH

V

OH

V

OL

V

OL

V

OL

V

OL

V

OL

V

OL

V

OL

Input t and t = 20 ns

TLH THL

MC14024B

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7

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC14024B

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8

P ACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035
––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

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