Datasheet MC14022BCP, MC14022BD, MC14022BDR2 Datasheet (MOTOROLA)

MC14022B

Octal Counter

The MC14022B is a four–stage Johnson octal counter with built–in code converter. High–speed operation and spike–free outputs are obtained by use of a Johnson octal counter design. The eight decoded outputs are normally low, and go high only at their appropriate octal time period. The output changes occur on the positive–going edge of the clock pulse. This part can be used in frequency division applications as well as octal counter or octal decode display applications.

• Fully Static Operation

• DC Clock Input Circuit Allows Slow Rise Times

• Carry Out Output for Cascading

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

• Pin–for–Pin Replacement for CD4022B

• Triple Diode Protection on All Inputs

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C Lead Temperature

L

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 2.)

(8–Second Soldering)

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14022BCP

AWLYYWW

1

16

14022B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14022BCP PDIP–16 2000/Box MC14022BD SOIC–16 2400/Box MC14022BDR2 SOIC–16 2500/Tape & Reel

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

SS

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

v (Vin or V

SS

or VDD). Unused outputs must be left open.

) v VDD.

out

should be constrained

out

1 Publication Order Number:

MC14022B/D

MC14022B

PIN ASSIGNMENT

CLOCK

CLOCK ENABLE

RESET

V

= PIN 16

DD

= PIN 8

V

SS

NC = PIN 6, 9

BLOCK DIAGRAM

14

13

15

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

C

out

Q1

1

Q0

2

Q2

3

Q5

4

Q6

NC

6

Q3

7

V

8

SS

V

16

DD

R

15

C

14 13

CE

125

C

out

Q4

11

Q7

10

NC

9

NC = NO CONNECTION

FUNCTIONAL TRUTH TABLE

(Positive Logic)

2 1 3

Clock Enable Reset Output=n

7 11

4 5

10 12

X = Don’t Care. If n < 4 Carry = 1, Otherwise = 0.

Clock

0X0 n X10 n

0 0 n+1

X0 n 1 0 n+1 X0n XX1Q0

CLOCK

14

13 CLOCK ENABLE

15 RESET

LOGIC DIAGRAM

V

DD

V

SS

11 1 5 7

Q4 Q1 Q6 Q3

C

Q

C

Q

D

R

Q0 Q5 Q2 Q7

24310

C

Q

C D

R

Q

C

Q

D

R

CARRY

C

Q

C

Q

D

R

12

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2

MC14022B

ÎÎÎ

V

DD

Î

ÎÎÎ

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

OL

OH

IL

IH

in

T

Vdc

5.0 10

Î

15

5.0 10

Î

15

Î

5.0 10

Î

15

Î

5.0 10

Î

15

Î

5.0

Î

10

Î

15

5.0 10

Î

15 15

—

Î

5.0 10

Î

15

5.0

Î

10 15

Î

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2 — —

Î

— —

Î

—

ООООООООООООООО

Characteristic

Output Voltage “0” Level

= VDD or 0

V

in

ОООООООО

“1” Level

V

= 0 or V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

ОООООООО

(V

OH

DD

= 4.5 or 0.5 Vdc) = 9.0 or 1.0 Vdc) = 13.5 or 1.5 Vdc)

“1” Level = 0.5 or 4.5 Vdc) = 1.0 or 9.0 Vdc) = 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source = 4.6 Vdc) = 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

= 50 pF on all outputs, all

(C

L

ОООООООО

buffers switching)

(4.) (5.)

Symbol

V

ÎÎ

V

ÎÎ

V

ÎÎ

V

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

C

ÎÎ

I

DD

ÎÎ

I

ÎÎ

SS

– 55_C

)

Max

0.05

Î

0.05 —

—

Î

—

Î

1.5

3.0

Î

4.0

Î

— —

Î

—

Î

— —

Î

—

Î

— —

—

Î

—

± 0.1

—

Î

5.0 10

Î

20

25_C

Min

— —

ÎÎ

—

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

ÎÎ

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4 — —

ÎÎ

— —

ÎÎ

—

(3.)

Typ

0 0

ÎÎ

0

5.0 10

ÎÎ

15

ÎÎ

2.25

4.50

ÎÎ

6.75

ÎÎ

2.75

5.50

ÎÎ

8.25

ÎÎ

– 4.2

– 0.88

ÎÎ

– 2.25

ÎÎ

– 8.8

0.88

2.25

ÎÎ

8.8

±0.00001

5.0

ÎÎ

0.005

0.010

ÎÎ

0.015

IT = (0.28 µA/kHz)f + I IT = (0.56 µA/kHz)f + I IT = (0.85 µA/kHz)f + I

Max

0.05

Î

0.05 —

—

Î

—

Î

1.5

3.0

Î

4.0

Î

— —

Î

—

Î

— —

Î

—

Î

— —

—

Î

—

± 0.1

7.5

Î

5.0 10

Î

20

DD DD DD

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

Î

3.5

7.0

Î

11

Î

– 1.7

– 0.36

Î

– 0.9

Î

– 2.4

0.36

0.9

Î

2.4 — —

Î

— —

Î

—

125_C

Max

0.05

Î

0.05

Î

± 1.0

Î

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.00125.

T

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

150 300 600

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

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3

MC14022B

Î

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(6.)

(C

= 50 pF, T

L

Output Rise and Fall Time

t

, t

TLH

t

ООООООООООООО

TLH

t

TLH

Propagation Delay Time

ООООООООООООО

Reset to Decode Output t

ООООООООООООО

PLH

t

PLH

ООООООООООООО

t

PLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

, t

= (1.7 ns/pF) CL + 415 ns

PHL

, t

= (0.66 ns/pF) CL + 197 ns

PHL

, t

= (0.5 ns/pF) CL + 150 ns

PHL

Propagation Delay Time

Clock to C

ООООООООООООО

t

PLH

ООООООООООООО

t

PLH

t

PLH

ООООООООООООО

out

, t

= (1.7 ns/pF) CL + 315 ns

PHL

, t

= (0.66 ns/pF) CL + 142 ns

PHL

, t

= (0.5 ns/pF) CL + 100 ns

PHL

Propagation Delay Time

Clock to Decode Output

ООООООООООООО

t

, t

PLH

t

PLH

ООООООООООООО

t

PLH

Turn–Off Delay Time

ООООООООООООО

Reset to C t

PLH

ООООООООООООО

t

PLH

ООООООООООООО

t

PLH

= (1.7 ns/pF) CL + 415 ns

PHL

, t

= (0.66 ns/pF) CL + 197 ns

PHL

, t

= (0.5 ns/pF) CL + 150 ns

PHL

out

= (1.7 ns/pF) CL + 315 ns = (0.66 ns/pF) CL + 142 ns = (0.5 ns/pF) CL + 100 ns

Clock Pulse Width

ООООООООООООО

Clock Frequency

ООООООООООООО

Reset Pulse Width

ООООООООООООО

Reset Removal Time

ООООООООООООО

Clock Input Rise and Fall Time

ООООООООООООО

Clock Enable Setup Time

ООООООООООООО

Clock Enable Removal Time

ООООООООООООО

= 25_C)

A

Symbol

ÎÎÎ

t

TLH

t

THL

ÎÎÎ

t

PLH

ÎÎÎ

t

PHL

ÎÎÎ

t

PLH

t

PHL

ÎÎÎ

t

PLH

t

PHL

ÎÎÎ

t

PLH

ÎÎÎ

t

WH

ÎÎÎ

f

cl

ÎÎÎ

t

WH

ÎÎÎ

t

rem

ÎÎÎ

t

, t

TLH

ÎÎÎ

t

su

ÎÎÎ

t

rem

ÎÎÎ

,

THL

V

DD

Vdc

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10 15

ÎÎ

5.0 10

ÎÎ

15

Min

ÎÎ

— —

ÎÎ

—

ÎÎ

—

ÎÎ

—

ÎÎ

—

ÎÎ

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

—

ÎÎ

—

ÎÎ

—

ÎÎ

—

250 100

ÎÎ

75 —

ÎÎ

— —

ÎÎ

500 250

ÎÎ

190 750

275

ÎÎ

210

ОООООООО

350 150 115

ÎÎ

420 200

ÎÎ

140

(7.)

Typ

ÎÎ

100

50

ÎÎ

40

ÎÎ

500

ÎÎ

230

ÎÎ

175

ÎÎ

400

ÎÎ

175 125

ÎÎ

275 125

ÎÎ

95

ÎÎ

400

ÎÎ

175

ÎÎ

125 125

50

ÎÎ

35

5.0

ÎÎ

12 16

ÎÎ

250 125

ÎÎ

95

375 135

ÎÎ

105

No Limit

175

75 52

ÎÎ

260 100

ÎÎ

70

Max

ÎÎ

200 100

ÎÎ

80

ÎÎ

1000

ÎÎ

460

ÎÎ

350

ÎÎ

800

ÎÎ

350 250

ÎÎ

1000

460

ÎÎ

350

ÎÎ

800

ÎÎ

350

ÎÎ

250

— —

ÎÎ

—

2.0

ÎÎ

5.0

6.7

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

—

— — —

ÎÎ

— —

ÎÎ

—

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

MHz

Î

ns

Î

ns

Î

—

Î

ns

Î

ns

Î

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4

MC14022B

V

DD

V

SS

V

DD

CLOCK ENABLE

A

RESET

S1

V

SS

B

CLOCK

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

C

out

V

SS

out

I

D

EXTERNAL

POWER

Outputs

Carry

VGS =– V VDS =V

Sink Drive

(S1 to A)

Clock to Q5

thru Q7

(S1 to B)

V

DD

V

out

SUPPLY

Figure 1. T ypical Output Source and Output Sink Characteristics Test Circuit

V

DD

Output

Source Drive

Clock to desired

Output

(S1 to B)

S1 to A

DD

– V

out

DD

500 µF

I

D

0.01 µF CERAMIC

Q0

CLOCK ENABLE

Q1 Q2

Q3 Q4

RESET

Q5 Q6

PULSE

GENERATOR

f

c

CLOCK

Q7

C

out

V

SS

CLCLCLCLCLCLCLCLC

L

Figure 2. T ypical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are

sequential within each stage and from stage to stage, with no dead time (except propagation delay).

CLOCK

C CE

Q0 Q1 Q6 Q7

R

MC14022B

•••

7 DECODED

OUTPUTS

C CE

Q0 Q1 Q6 Q7

R

MC14022B

•••

6 DECODED

OUTPUTS

C

MC14022B

CE

•••

Q1 Q6 Q7

6 DECODED

OUTPUTS

FIRST STAGE INTERMEDIATE STAGES LAST STAGE

Figure 3. Counter Expansion

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5

R

MC14022B

t

WH

CLOCK

CLOCK ENABLE

t

rem

RESET

t

PHL

Q0

t

PLH

Q1

t

PLH

Q2

Q3

Q4

Q5

Q6

Q7

C

out

t

PLH

t

WL

t

PHL

t

PLH

t

PHL

t

PHL

t

PLH

t

rel

20 ns 20 ns

t

PHL

t

PHL

TLH

t

PLH

t

PLH

t

THL

t

PHL

TLH

t

PHL

t

su

20 ns

t

PLH

20 ns

50%

90% 50%

t

TLH

t

TLH

t

PHL

t

PHL

t

THL

10%

t

TLH

t

TLH

t

TLH

20 ns

t

PLH

t

THL

t

PLH

90%

10%

50%

t

PHL

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

t

THL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

t

THL

Figure 4. AC Measurement Definition and Functional Waveforms

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6

–T–

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14022B

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77

G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74

M 0 10 0 10

S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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7

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14022B

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

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MC14022B/D

Datasheet MC14022BCP, MC14022BD, MC14022BDR2 Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual