Datasheet MC14014B, MC14021B Datasheet (ON Semiconductor)

MC14014B, MC14021B

8−Bit Static Shift Register

The MC14014B and MC14021B 8−bit static shift registers are
constructed with MOS P−channel and N−channel enhancement mode
devices in a single monolithic structure. These s hift registers f ind p rimary
use in parallel−to−serial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.

Features

• Synchronous Parallel Input/Serial Output (MC14014B)

• Asynchronous Parallel Input/Serial Output (MC14021B)

• Synchronous Serial Input/Serial Output

• Full Static Operation

• “Q” Outputs from Sixth, Seventh, and Eighth Stages

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• MC14014B Pin−for−Pin Replacement for CD4014B

• MC14021B Pin−for−Pin Replacement for CD4021B

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

Vin, V

Iin, I

P

T

T

T

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

DC Supply Voltage Range −0.5 to +18.0 V

DD

Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation, per Package

D

Ambient Temperature Range −55 to +125 °C

A

Storage Temperature Range −65 to +150 °C

stg

Lead Temperature

L

SS

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

(Note 1)

(8−Second Soldering)

 (Vin or V

or VDD). Unused outputs must be left open.

)  VDD.

out

)

SS

−0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

should be constrained

out

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B

SOEIAJ−16

F SUFFIX

CASE 966

xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

16

MC140xxBCP

AWLYYWW

1

16

140xxB

AWLYWW

1

16

MC140xxB

AWLYWW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 5

1 Publication Order Number:

MC14014B/D

MC14014B, MC14021B

TRUTH TABLE

SERIAL OPERATION:

t Clock D

S

n000??
n+1 1 0 1 0 ?
n+2 0 0 0 1 0
n+3 1 0 1 0 1

X 0 Q6 Q7 Q8

PARALLEL OPERATION:

MC14014B MC14021B D

*Q6, Q7, & Q8 are available externally
X = Don’t Care

Clock

Q6 Q7 Q8

P/S t=n+6 t=n+7 t=n+8

P/S Pn*Q

S

n

XX100
XX111

P/S

D

PIN ASSIGNMENT

1

P8

2

Q6

3

Q8

4

P4

P3

6

P2

7

P1

8

V

SS

V

16

DD

P7

15

P6

14

P5

13

Q7

125

D

11

S

C

10

P/S

9

LOGIC DIAGRAM

P1 P2 P3 P6 P7 P8

9

11

S

765 14151

DCQDCQDCQD

QDCQD

CLOCK

C

Q Q

CQ

10

V

DD

V

SS

= PIN 16

= PIN 8

P4 = PIN 4
P5 = PIN 13

2123

Q8Q7Q6

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2

MC14014B, MC14021B

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

ОООООООО

Output Voltage “0” Level

V

= VDD or 0

in

ОООООООО

Vin = 0 or V

ОООООООО

DD

“1” Level

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

ОООООООО

O

= 9.0 or 1.0 Vdc)

(V

O

ОООООООО

= 13.5 or 1.5 Vdc)

(V

O

(VO = 0.5 or 4.5 Vdc) “1” Level

= 1.0 or 9.0 Vdc)

(V

ОООООООО

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

ОООООООО

(V

= 2.5 Vdc) Source

OH

(V

= 4.6 Vdc)

OH

ОООООООО

ОООООООО

(V

OH

(V

OH

= 9.5 Vdc)
= 13.5 Vdc)

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current
Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current (Notes 3 & 4)

ОООООООО

(Dynamic plus Quiescent,
Per Package)

ОООООООО

(C

= 50 pF on all outputs, all

L

ОООООООО

buffers switching)

Symbol

ÎÎ

V

OL

ÎÎ

V

OH

ÎÎ

V

IL

ÎÎ

ÎÎ

V

IH

ÎÎ

I

OH

ÎÎ

ÎÎ

ÎÎ

I

OL

ÎÎ

I

in

C

in

ÎÎ

I

DD

ÎÎ

I

T

ÎÎ

ÎÎ

ÎÎ

V

DD

Vdc

Î

5.0
10
15

Î

5.0
10

Î

15

5.0

Î

10

Î

15

5.0
10

Î

15

Î

5.0

5.0

Î

10

Î

15

5.0
10

Î

15
15

−

Î

5.0
10

Î

15

5.0

Î

10
15

Î

Î

Min

Î

−

−

−

Î

4.95

9.95

Î

14.95

−

Î

−

Î

−

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2

−

−

Î

−

−

Î

−

ООООООООООООООО

ООООООООООООООО

ООООООООООООООО

SS

− 55C

)

Max

Î

0.05

0.05

0.05

Î

Î

1.5

Î

3.0

Î

4.0

Î

Î

Î

Î

Î

± 0.1

Î

5.0
10

Î

15

−

−

−

−

−

−

−

−

−

−

−

−

−

−

25C

Min

ÎÎ

−

−

−

ÎÎ

4.95

9.95

ÎÎ

14.95

−

ÎÎ

−

ÎÎ

−

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

− 1.3

ÎÎ

− 3.4

0.51

1.3

ÎÎ

3.4

−

−

ÎÎ

−

−

ÎÎ

−

Typ

(Note 2)

Î

0
0
0

Î

5.0
10

Î

15

2.25

Î

4.50

Î

6.75

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

− 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.005

0.010

Î

0.015

IT = (0.75 A/kHz) f + I
IT = (1.50 A/kHz) f + I
IT = (2.25 A/kHz) f + I

Max

ÎÎ

0.05

0.05

0.05

ÎÎ

−

−

ÎÎ

−

1.5

ÎÎ

3.0

ÎÎ

4.0

−

−

ÎÎ

−

ÎÎ

−

−

ÎÎ

−

ÎÎ

−

−

−

ÎÎ

−

± 0.1

7.5

ÎÎ

5.0
10

ÎÎ

15

DD
DD
DD

Min

Î

−

−

−

Î

4.95

9.95

Î

14.95

−

Î

−

Î

−

3.5

7.0

Î

11

Î

– 1.7

− 0.36

Î

– 0.9

Î

− 2.4

0.36

0.9

Î

2.4

−

−

Î

−

−

Î

−

125C

Max

Î

0.05

0.05

0.05

Î

Î

1.5

Î

3.0

Î

4.0

Î

Î

Î

Î

Î

± 1.0

Î

150
300

Î

600

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25C.

4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL − 50) Vfk

I

T(CL

where: I

is in A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.0015.

T

Unit

Î

Vdc

Î

−

Vdc

−

Î

−
Vdc

Î

Î

−

Vdc

−

Î

−

mAdc

Î

−

−

Î

−

Î

−

−

mAdc

−

Î

−

Adc

−

pF

Î

Adc

Î

Adc

Î

Î

Î

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3

MC14014B, MC14021B

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

SWITCHING CHARACTERISTICS (Note 5) (C

= 50 pF, T

L

Characteristic

ООООООООООООО

Output Rise and Fall Time

, t

t

TLH

ООООООООООООО

t

TLH

t

TLH

ООООООООООООО

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time (Clock to Q, P/S to Q)

, t

t

PHL

ООООООООООООО

t

PHL

ООООООООООООО

t

PHL

= (1.7 ns/pF) CL + 315 ns

PLH

, t

= (0.66 ns/pF) CL + 137 ns

PLH

, t

= (0.5 ns/pF) CL + 90 ns

PLH

Clock Pulse Width

ООООООООООООО

Clock Frequency

ООООООООООООО

ООООООООООООО

Parallel/Serial Control Pulse Width

ООООООООООООО

Setup Time

ООООООООООООО

P/S to Clock

ООООООООООООО

Hold Time

Clock to P/S

ООООООООООООО

Setup Time

ООООООООООООО

Data (Parallel or Serial) to

Clock or P/S

ООООООООООООО

Hold Time

Clock to D

ООООООООООООО

s

Hold Time

ООООООООООООО

Clock to P

ООООООООООООО

n

Input Clock Rise Time

ООООООООООООО

= 25C)

A

Symbol

ÎÎÎ

t

,

TLH

t

THL

ÎÎÎ

ÎÎÎ

t

,

PLH

t

PHL

ÎÎÎ

ÎÎÎ

t

WH

ÎÎÎ

f

cl

ÎÎÎ

ÎÎÎ

t

WH

ÎÎÎ

t

su

ÎÎÎ

ÎÎÎ

t

h

ÎÎÎ

t

su

ÎÎÎ

ÎÎÎ

t

h

ÎÎÎ

t

h

ÎÎÎ

ÎÎÎ

t

r(cl)

ÎÎÎ

V

DD

Vdc

ÎÎ

5.0

ÎÎ

10
15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

5.0
10

ÎÎ

15

5.0

ÎÎ

10

ÎÎ

15

5.0
10

ÎÎ

15

5.0

ÎÎ

10
15

ÎÎ

5.0
10

ÎÎ

15

5.0

ÎÎ

10
15

ÎÎ

5.0
10

ÎÎ

15

5.0

ÎÎ

10
15

ÎÎ

5.0
10

ÎÎ

15

Min

ÎÎ

−

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

−

ÎÎ

400
175

ÎÎ

135

−

ÎÎ

−

−

ÎÎ

400
175

ÎÎ

135
200

ÎÎ

100

80

ÎÎ

20
20

ÎÎ

25

350

ÎÎ

80
60

ÎÎ

45
35

ÎÎ

35
50

ÎÎ

45
45

ÎÎ

−

−

ÎÎ

−

Typ

(Note 6)

ÎÎ

100

ÎÎ

50
40

ÎÎ

400

ÎÎ

170

ÎÎ

115
150

75

ÎÎ

40

3.0

ÎÎ

6.0

ÎÎ

8.0

150

75

ÎÎ

40

100

ÎÎ

50
40

ÎÎ

– 2.5

– 10

ÎÎ

0

150

ÎÎ

50
30

ÎÎ

0
0

ÎÎ

5

25

ÎÎ

20
20

ÎÎ

−

−

ÎÎ

−

Max

ÎÎ

200

ÎÎ

100

80

ÎÎ

800

ÎÎ

340

ÎÎ

230

−

−

ÎÎ

−

1.5

ÎÎ

3.0

ÎÎ

4.0

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

−

−

ÎÎ

15

5

ÎÎ

4

5. The formulas given are for the typical characteristics only at 25C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

Î

ns

Î

Î

ns

Î

Î

ns

Î

MHz

Î

Î

ns

Î

ns

Î

Î

ns

Î

ns

Î

Î

ns

Î

ns

Î

Î

s

Î

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4

MC14014B, MC14021B

PULSE

GENERATOR

P/S
C

P6
P7
P8
D

V

DD

Q6

Q7

Q8

S

V

out

EXTERNAL

POWER
SUPPLY

V

DD

P/S

PULSE

GENERATOR

I

OH

C
P6

P7
P8
D

Q6

Q7

Q8

S

V

out

I

OL

EXTERNAL

POWER
SUPPLY

Preset output under test to a logic “1” level.

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

V

DD

500 FI

PULSE

GENERATOR 1

PULSE

GENERATOR 2

P/S
C

P1
P2

P3
P4
P5

P6
P7

P8
D

D

0.01 F
CERAMIC

Q6

C

L

Q7

C

L

Q8

S

C

V

SS

L

1

f

CLOCK

50%

DATA

Figure 3. Power Dissipation Test Circuit and Waveform

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5

SW 1

V

PULSE

GENERATOR 1

PULSE

GENERATOR 2

11

SWITCH POSITION 1 = PARALLEL IN
SWITCH POSITION 2 = SERIAL IN

MC14014B, MC14021B

DD

1

2

22

Figure 4. Switching Time Test Circuit and Waveforms

P/S
C

P1
P2
P3
P4
P5
P6
P7
P8
D

V

DD

PARALLEL OR

SERIAL DATA

Q6

Q7

C

L

INPUT

CLOCK OR P/S

Q8

S

V

SS

SW 2

INPUT

Q

OUTPUT

20 ns 20 ns

V

t

PHL

DD

V

SS

V

DD

V

SS

V

OH

V

OL

90%
50%

10%

t

su

t

WH

90%
50%
10%

t

WH

t

PLH

90%
50%
10%

t

TLH

t

THL

t

WL

t

THL

tWL = tWH = 50% DUTY CYCLE

ORDERING INFORMATION

Device Package Shipping

MC14014BCP PDIP−16 500 Units / Rail
MC14014BCPG PDIP−16

500 Units / Rail

(Pb−Free)
MC14014BD SOIC−16 48 Units / Rail
MC14014BDG SOIC−16

48 Units / Rail

(Pb−Free)
MC14014BDR2 SOIC−16 2500 Units / Tape & Reel
MC14014BDR2G SOIC−16

2500 Units / Tape & Reel

(Pb−Free)
MC14014BF SOEIAJ−16 50 Units / Rail
MC14014BFEL SOEIAJ−16 2000 Units / Tape & Reel

MC14021BCP PDIP−16 500 Units / Rail
MC14021BCPG PDIP−16

500 Units / Rail

(Pb−Free)
MC14021BD SOIC−16 48 Units / Rail
MC14021BDG SOIC−16

48 Units / Rail

(Pb−Free)
MC14021BDR2 SOIC−16 2500 Units / Tape & Reel
MC14021BDR2G SOIC−16

2500 Units / Tape & Reel

(Pb−Free)
MC14021BF SOEIAJ−16 50 Units / Rail
MC14021BFEL SOEIAJ−16 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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6

MC14014B, MC14021B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

−A−

916

B

18

F

C

S

SEATING

−T−

PLANE

H

G

D

16 PL

0.25 (0.010) T

K

M

A

L

J

M

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77

M

G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

M

S

X 45

R



F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

http://onsemi.com

7

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC14014B, MC14021B

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE O

L

E

M



L

DETAIL P

VIEW P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

Q

1

c

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L
L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

INCHES

10



10

0





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MC14014B/D

8