Datasheet MC14015BFEL, MC14015BFL1, MC14015BFL2, MC14015BFR1, MC14015BCP Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14015B/D

MC14015B

Dual 4-Bit Static
Shift Register

The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

http://onsemi.com

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14015BCP PDIP–16 2000/Box
MC14015BD SOIC–16 48/Rail
MC14015BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14015BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14015B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14015B

AWLYWW

TSSOP–16
DT SUFFIX

CASE 948F

14

015B

ALYW

1

16

MC14015BDT TSSOP–16 2000/Tape & Reel
MC14015BF SOEIAJ–16 See Note 1.
MC14015BFEL SOEIAJ–16 See Note 1.

MC14015B

http://onsemi.com

2

TRUTH TABLE

C D R Q0 Q

n

0 0 0 Q

n–1

1 0 1 Q

n–1

X 0 No Change No Change

X X 1 0 0

X = Don’t Care
Q

n

= Q0, Q1, Q2, or Q3, as applicable.

Q

n–1

= Output of prior stage.

BLOCK DIAGRAM

14

1

15

6

9

7

5
4
3
10

13
12
11
2

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

D

C

R

R

D

C

V

DD

= PIN 16

V

SS

= PIN 8

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q1

B

Q0

B

R

B

D

B

V

DD

C

A

Q3

A

Q2

B

Q1

A

Q2

A

Q3

B

C

B

V

SS

D

A

R

A

Q0

A

MC14015B

http://onsemi.com

3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

Vin = 0 or V

DD

“1” Level

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or .05 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

(VO = 0.5 or 4.5 Vdc) “1” Level
(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

– 4.2
– 0.88
– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

mAdc

ОООООООО

Î

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

0.64

1.6

4.2

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

0.51

1.3

3.4

Î

Î

Î

Î

0.88

2.25

8.8

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.36

0.9

2.4

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

(V

in

= 0)

C

in

—

—

—

—

5.0

7.5

—

—

pF

ОООООООО

Î

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

ÎÎ

Î

I

DD

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

5.0
10
20

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.005

0.010

0.015

ÎÎ

Î

ÎÎ

Î

5.0
10
20

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

150
300
600

Î

Î

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (1.2 µA/kHz)f + I

DD

IT = (2.4 µA/kHz)f + I

DD

IT = (3.6 µA/kHz)f + I

DD

Î

Î

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14015B

http://onsemi.com

4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time

Clock, Data to Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 225 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 92 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 65 ns

Reset to Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 375 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 147 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 95 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

5.0
10
15

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

—
—
—

—
—
—

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

310
125

90

460
180
120

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

750
250
170

750
250
170

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

400
175
135

ÎÎ

Î

185

85
55

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Clock Pulse Frequency

ÎÎÎ

Î

ÎÎÎ

Î

f

cl

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

2.0

6.0

7.5

ÎÎ

Î

ÎÎ

Î

1.5

3.0

3.75

Î

Î

Î

Î

MHz

ООООООООООООО

Î

Clock Pulse Rise and Fall Times

ÎÎÎ

Î

t

TLH

, t

THL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

—
—
—

ÎÎ

Î

15

5
4

Î

Î

µs

ООООООООООООО

Î

Reset Pulse Width

ÎÎÎ

Î

t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

400
160
120

ÎÎ

Î

200

80
60

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Setup Time

ÎÎÎ

Î

ÎÎÎ

Î

t

su

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

350
100

75

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

7. The formulas given are for typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

2

CLOCK

DATA

50%

1

f

PULSE

GENERATOR

1

500 µF

V

DD

I

D

0.01 µF
CERAMIC

C

L

Q0
Q1
Q2
Q3

D

C

R

V

SS

C

L

C

L

C

L

V

DD

MC14015B

http://onsemi.com

5

Figure 2. Switching Test Circuit and Waveforms

V

DD

C

L

V

SS

PULSE

GENERATOR

2

PULSE

GENERATOR

1

Q0
Q1
Q2
Q3

D

C

R

C

L

C

L

C

L

DATA

INPUT

CLOCK

INPUT

t

TLH

t

THL

V

DD

0 V

V

DD

0 V

t

su

t

TLH

t

THL

t

WH

t

WL

Q0

t

TLH

t

THL

t

PLH

t

PHL

90%

50%

10%

90%

50%

10%

90%

50%

10%

t

WL

= tWH = 50% Duty Cycle

t

TLH

= t

THL

≤ 20 ns

SYNC

t–

Figure 3. Setup and Hold Time Test Circuit and Waveforms

V

DD

C

L

V

SS

PULSE

GENERATOR

2

PULSE

GENERATOR

1

Q0
Q1
Q2
Q3

D

C

R

C

L

C

L

C

L

SYNC

CLOCK

INPUT

DATA

INPUT

50%

V

DD

0 V

V

DD

0 V

t

su

t

h

50%

MC14015B

http://onsemi.com

6

CIRCUIT SCHEMA TICS

DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

SINGLE BIT

Q

V

DD

V

SS

TO D OF

NEXT BIT

DATA

IN

CLOCK

RESET

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

DATA

IN

RESET

IN

CLOCK

IN

CLOCK

TO 4 BITS

RESET

TO 4 BITS

DATA TO

FIRST BIT

MC14015B

http://onsemi.com

7

LOGIC DIAGRAMS

SINGLE BIT

DATA

RESET

C

C

C

C

C

C

C

C

C

C

C

Q
TO D OF

NEXT BIT

COMPLETE DEVICE

D

C

R

D

C

R

14

1

15

6

9

7

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

54310

Q0 Q1 Q2 Q3

D
C

R

Q
Q

D
C

R

Q
Q

D
C

R

Q
Q

D
C

R

Q
Q

11 21213

Q0 Q1 Q2 Q3

D
C

R

Q
Q

D
C

R

Q
Q

D
C

R

Q
Q

D
C

R

Q
Q

VDD = PIN 16

V

SS

= PIN 8

MC14015B

http://onsemi.com

8

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

MC14015B

http://onsemi.com

9

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14015B

http://onsemi.com

10

P ACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC14015B

http://onsemi.com

11

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14015B

http://onsemi.com

12

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support

Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

MC14015B/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–[e-mail]

French Phone: [phone] (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[e-mail]

English Phone: [phone] (M–F 12:00pm to 5:00pm UK T ime)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy , England, Ireland