Datasheet MC14013BFL2, MC14013BFR1, MC14013BFR2, MC14013BDT, MC14013BDTR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14013B/D

MC14013B

Dual Type D Flip-Flop

The MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q

). These devices may be used as shift register

elements or as type T flip–flops for counter and toggle applications.

• Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge–Clocked Flip–Flop Design

Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4013B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14013BCP PDIP–14 2000/Box
MC14013BD SOIC–14

55/Rail
MC14013BDR2 SOIC–14 2500/Tape & Reel
MC14013BDT TSSOP–14

MC14013BF SOEIAJ–14

96/Rail

See Note 1.

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14013BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14
DT SUFFIX

CASE 948G

1

14

14013B

AWLYWW

14

013B

ALYW

1

14

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14013B

AWLYWW

MC14013BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

MC14013BDTR2 TSSOP–14 2500/Tape & Reel

MC14013B

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2

TRUTH TABLE

Inputs Outputs

Clock†Data Reset Set Q Q

0 0 0 0 1
1 0 0 1 0

X 0 0 Q Q
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1

X = Don’t Care
† = Level Change

BLOCK DIAGRAM

10

11

9

8

4

3

5

6

12

13

2

1

S

S

R

R

D

C

D

C

Q

Q

Q

Q

VDD = PIN 14

V

SS

= PIN 7

11

12

13

14

8

9

105

4

3

2

1

7

6

R

B

C

B

Q

B

Q

B

V

DD

S

B

D

B

R

A

C

A

Q

A

Q

A

V

SS

S

A

D

A

PIN ASSIGNMENT

No
Change

MC14013B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Î

Output Voltage “0” Level

V

in

= VDD or 0

ÎÎ

Î

V

OL

Î

Î

5.0
10
15

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

ÎÎ

Î

—
—
—

Î

Î

0
0
0

ÎÎ

Î

0.05

0.05

0.05

Î

Î

—
—
—

Î

Î

0.05

0.05

0.05

Î

Î

Vdc

ОООООООО

Î

Vin = 0 or V

DD

“1” Level

ÎÎ

Î

V

OH

Î

Î

5.0
10
15

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

ÎÎ

Î

4.95

9.95

14.95

Î

Î

5.0
10
15

ÎÎ

Î

—
—
—

Î

Î

4.95

9.95

14.95

Î

Î

—
—
—

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

2.25

4.50

6.75

ÎÎ

Î

ÎÎ

Î

1.5

3.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.5

3.0

4.0

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

(VO = 0.5 or 4.5 Vdc) “1” Level
(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

V

IH

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

3.5

7.0
11

Î

Î

Î

Î

2.75

5.50

8.25

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

3.5

7.0
11

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

Vdc

ОООООООО

Î

ОООООООО

Î

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OH

Î

Î

Î

Î

5.0

5.0
10
15

Î

Î

Î

Î

– 3.0

– 0.64

– 1.6
– 4.2

Î

Î

Î

Î

—
—
—
—

ÎÎ

Î

ÎÎ

Î

– 2.4

– 0.51

– 1.3
– 3.4

Î

Î

Î

Î

– 4.2
– 0.88
– 2.25

– 8.8

ÎÎ

Î

ÎÎ

Î

—
—
—
—

Î

Î

Î

Î

– 1.7

– 0.36

– 0.9
– 2.4

Î

Î

Î

Î

—
—
—
—

Î

Î

Î

Î

mAdc

ОООООООО

Î

ОООООООО

Î

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

ÎÎ

Î

ÎÎ

Î

I

OL

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

0.64

1.6

4.2

Î

Î

Î

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

0.51

1.3

3.4

Î

Î

Î

Î

0.88

2.25

8.8

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.36

0.9

2.4

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

(V

in

= 0)

C

in

—

—

—

—

5.0

7.5

—

—

pF

ОООООООО

Î

ОООООООО

Î

Quiescent Current

(Per Package)

ÎÎ

Î

ÎÎ

Î

I

DD

Î

Î

Î

Î

5.0
10
15

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

1.0

2.0

4.0

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

0.002

0.004

0.006

ÎÎ

Î

ÎÎ

Î

1.0

2.0

4.0

Î

Î

Î

Î

—
—
—

Î

Î

Î

Î

30
60

120

Î

Î

Î

Î

µAdc

ОООООООО

Î

ОООООООО

Î

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

ÎÎ

Î

ÎÎ

Î

I

T

Î

Î

Î

Î

5.0
10
15

ООООООООООООООО

Î

ООООООООООООООО

Î

IT = (0.75 µA/kHz) f + I

DD

IT = (1.5 µA/kHz) f + I

DD

IT = (2.3 µA/kHz) f + I

DD

Î

Î

Î

Î

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14013B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Î

ООООООООООООО

Î

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

100

50
40

ÎÎ

Î

ÎÎ

Î

200
100

80

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Propagation Delay Time

Clock to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 90 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 42 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 25 ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

t

PHL

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

175

75
50

ÎÎ

Î

ÎÎ

Î

350
150
100

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Set to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 90 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 42 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 25 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

175

75
50

ÎÎ

Î

ÎÎ

Î

350
150
100

Î

Î

Î

Î

ООООООООООООО

Î

ООООООООООООО

Î

Reset to Q, Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 265 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 67 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 50 ns

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

—
—
—

ÎÎ

Î

ÎÎ

Î

225
100

75

ÎÎ

Î

ÎÎ

Î

450
200
150

Î

Î

Î

Î

ООООООООООООО

Î

Setup Times

(9.)

ÎÎÎ

Î

t

su

ÎÎ

Î

5.0
10
15

ÎÎ

Î

40
20
15

ÎÎ

Î

20
10

7.5

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Hold Times

(9.)

ÎÎÎ

Î

ÎÎÎ

Î

t

h

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

40
20
15

ÎÎ

Î

ÎÎ

Î

20
10

7.5

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Width

ÎÎÎ

Î

tWL, t

WH

ÎÎ

Î

5.0
10
15

ÎÎ

Î

250
100

70

ÎÎ

Î

125

50
35

ÎÎ

Î

—
—
—

Î

Î

ns

ООООООООООООО

Î

Clock Pulse Frequency

ÎÎÎ

Î

f

cl

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

4.0
10
14

ÎÎ

Î

2.0

5.0

7.0

Î

Î

MHz

ООООООООООООО

Î

Clock Pulse Rise and Fall Time

ÎÎÎ

Î

t

TLH

t

THL

ÎÎ

Î

5.0
10
15

ÎÎ

Î

—
—
—

ÎÎ

Î

—

—

—

ÎÎ

Î

15

5.0

4.0

Î

Î

µs

ООООООООООООО

Î

ООООООООООООО

Î

Set and Reset Pulse Width

ÎÎÎ

Î

ÎÎÎ

Î

tWL, t

WH

ÎÎ

Î

ÎÎ

Î

5.0
10
15

ÎÎ

Î

ÎÎ

Î

250
100

70

ÎÎ

Î

ÎÎ

Î

125

50
35

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

ООООООООООООО

Î

Removal Times

Set

ÎÎÎ

Î

ÎÎÎ

Î

t

rem

ÎÎ

Î

ÎÎ

Î

5
10
15

ÎÎ

Î

ÎÎ

Î

80
45
35

ÎÎ

Î

ÎÎ

Î

0
5
5

ÎÎ

Î

ÎÎ

Î

—
—
—

Î

Î

Î

Î

ns

ООООООООООООО

Î

Reset

ÎÎÎÎÎÎ

Î

5
10
15

ÎÎ

Î

50
30
25

ÎÎ

Î

– 35
– 10

– 5

ÎÎ

Î

—
—
—

Î

Î

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM (1/2 of Device Shown)

R

C

D

S

C

C

CC

C

C

C

C

C

C

Q

Q

MC14013B

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5

Figure 1. Dynamic Signal Waveforms

(Data, Clock, and Output)

Figure 2. Dynamic Signal Waveforms

(Set, Reset, Clock, and Output)

20 ns 20 ns

D

C

Q

90%

50%

10%

t

su

(H)

t

su (L)

t

h

t

WH

t

WL

90%

50%

10%

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

t

TLH

t

THL

t

PHL

t

PLH

90%

50%
10%

Inputs R and S low.

1

f

cl

20 ns 20 ns

SET OR

RESET

CLOCK

Q OR Q

90%

50%

10%

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

20 ns

20 ns

t

rem

90%

50%

10%

50%

t

PLH

t

PHL

t

w

20 ns

t

w

TYPICAL APPLICATIONS

n–STAGE SHIFT REGISTER

BINARY RIPPLE UP–COUNTER (Divide–by–2

n

)

MODIFIED RING COUNTER (Divide–by–(n+1))

D

CLOCK

n

th

21

QD

C

Q
Q

D
C

Q

Q

D
C

Q
Q

CLOCK

n

th

21

D
C

Q
Q

D
C

Q
Q

D
C

Q
Q

Q

T FLIP–FLOP

n

th

21

QD

C

Q
Q

D
C

Q
Q

D
C

Q
Q

CLOCK

MC14013B

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6

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC14013B

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7

P ACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035
––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L
DETAIL P

M

A

b
c
D
E
e

0.50

M

Z

MC14013B

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