Datasheet MC14012BF, MC14012BCP, MC14012BD, MC14012BDR2, MC14012BFEL Datasheet (MOTOROLA)

MC14012B

B-Suffix Series CMOS Gates

The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range.

• Double Diode Protection on All Inputs

• Pin–for–Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

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14

PDIP–14

P SUFFIX

CASE 646

MARKING

DIAGRAMS

MC14012BCP

AWLYYWW

1

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C
Lead Temperature

L

SS

or VDD). Unused outputs must be left open.

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

14

SOIC–14

D SUFFIX

CASE 751A

SOEIAJ–14

F SUFFIX

CASE 965

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

14012B

AWLYWW

1

14

MC14012B

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14012BCP PDIP–14 2000/Box
MC14012BD SOIC–14
MC14012BDR2 SOIC–14 2500/Tape & Reel
MC14012BF SOEIAJ–14 See Note 1.

55/Rail

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 3

MC14012BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

1 Publication Order Number:

MC14012B/D

MC14012B

V

DD

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

MC14012B

Dual 4–Input NAND Gate

1

OUT

A

2

IN 1

A

3

IN 2

A

4

IN 3

A

IN 4

A

6

NC

7

V

SS

NC = NO CONNECTION

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

Output Voltage “0” Level

ОООООООО

V

= VDD or 0

in

ОООООООО

V

= 0 or V

in

ОООООООО

DD

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

ОООООООО

(V

= 9.0 or 1.0 Vdc)

O

ОООООООО

= 13.5 or 1.5 Vdc)

(V

O

(V

= 0.5 or 4.5 Vdc)

O

ОООООООО

= 1.0 or 9.0 Vdc)

(V

O

ОООООООО

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

ОООООООО

(V

= 4.6 Vdc)

OH

ОООООООО

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

ОООООООО

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

ОООООООО

OL

Input Current
Input Capacitance

(V

= 0)

in

ОООООООО

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

(Dynamic plus Quiescent,

ОООООООО

Per Gate, C

= 50 pF)

L

“1” Level

“1” Level

(5.) (6.)

14

V

13

OUT

12

IN 4

11

IN 3
IN 2

105

9

IN 1

8

NC

Symbol

V

OL

ÎÎ

ÎÎ

V

OH

ÎÎ

V

IL

ÎÎ

ÎÎ

V

IH

ÎÎ

ÎÎ

I

OH

ÎÎ

ÎÎ

ÎÎ

I

OL

ÎÎ

I

in

C

in

ÎÎ

I

DD

ÎÎ

I

T

ÎÎ

DD

B
B
B
B
B

)

SS

V
Vdc

5.0

Î

10
15

Î

5.0
10

Î

15

5.0

Î

10

Î

15

5.0

Î

10

Î

15

5.0

Î

5.0

Î

10
15

Î

5.0
10
15

Î

15
—

Î

5.0
10
15

Î

5.0
10

Î

15

– 55_C

Min

—

Î

—
—

Î

4.95

9.95

Î

14.95

—

Î

—

Î

—

3.5

Î

7.0

Î

11

– 3.0

Î

– 0.64

Î

– 1.6
– 4.2

Î

0.64

1.6

4.2

Î

—
—

Î

—
—
—

Î

Max

0.05

Î

0.05

0.05

Î

Î

1.5

Î

3.0

Î

4.0

Î

Î

Î

Î

Î

Î

± 0.1

Î

0.25

0.5

1.0

Î

Min

ÎÎ

ÎÎ

—
—
—

—
—
—

—
—
—
—

—

4.95

9.95

ÎÎ

14.95

ÎÎ

ÎÎ

ÎÎ

ÎÎ

– 2.4

ÎÎ

– 0.51

ÎÎ

– 1.3
– 3.4

ÎÎ

0.51
—
—

ÎÎ

—

ÎÎ

ÎÎ

IT = (0.3 µA/kHz) f + IDD/N

ООООООООООООООО

I
I

2
3

4
5

9

10
11

12

V

= PIN 14

DD

= PIN 7

V

SS

25_C

(4.)

Typ

—
—
—

0

Î

0
0

Î

ÎÎ

ÎÎ

5.0
10

—
—
—

3.5

7.0
11

Î

2.25

Î

4.50

Î

6.75

2.75

Î

5.50

Î

8.25

– 4.2

Î

– 0.88

Î

– 2.25

– 8.8

Î

15

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

0.88

1.3

3.4
—
—

—
—
—

= (0.6 µA/kHz) f + IDD/N

T

= (0.9 µA/kHz) f + IDD/N

T

2.25

8.8

Î

±0.00001

5.0

Î

0.0005

0.0010

0.0015

Î

ÎÎ

± 0.1

ÎÎ

ÎÎ

NC = 6, 8

Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

7.5

0.25

0.5

1.0

1

13

Min

—

Î

—
—

Î

4.95

9.95

Î

14.95

—

Î

—

Î

—

3.5

Î

7.0

Î

11

– 1.7

Î

– 0.36

Î

– 0.9
– 2.4

Î

0.36

0.9

2.4

Î

—
—

Î

—
—
—

Î

125_C

Max

0.05

Î

0.05

0.05

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

± 1.0

Î

Î

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk

I

T(CL

where: I

is in µA (per package), CL in pF , V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per

T

package.

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

—

7.5
15
30

Unit

Vdc

Î

Î

Vdc

Î

Vdc

Î

Î

Vdc

Î

Î

mAdc

Î

Î

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

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2

MC14012B

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

B–SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(7.)

(C

L

= 50 pF, T

Output Rise Time

t

= (1.35 ns/pF) CL + 33 ns

TLH

ООООООООООООО

= (0.60 ns/pF) CL + 20 ns

t

TLH

ООООООООООООО

t

= (0.40 ns/PF) CL + 20 ns

TLH

Output Fall Time

t

= (1.35 ns/pF) CL + 33 ns

ООООООООООООО

THL

= (0.60 ns/pF) CL + 20 ns

t

THL

ООООООООООООО

t

= (0.40 ns/pF) CL + 20 ns

THL

Propagation Delay Time

ООООООООООООО

t

, t

PLH

t

PLH

ООООООООООООО

t

PLH

= (0.90 ns/pF) CL + 115 ns

PHL

, t

= (0.36 ns/pF) CL + 47 ns

PHL

, t

= (0.26 ns/pF) CL + 37 ns

PHL

= 25_C)

A

ÎÎÎ

Symbol

t

TLH

ÎÎÎ

ÎÎÎ

t

THL

ÎÎÎ

ÎÎÎ

t

, t

PLH

ÎÎÎ

ÎÎÎ

PHL

V

DD

ÎÎ

Vdc

5.0

ÎÎ

10

ÎÎ

15

ÎÎ

5.0
10

ÎÎ

15

ÎÎ

5.0
10

ÎÎ

15

ÎÎ

Min

—

ÎÎ

—

ÎÎ

—

ÎÎ

—
—

ÎÎ

—

ÎÎ

—
—

ÎÎ

—

ÎÎ

(8.)

Typ

100

ÎÎ

50

ÎÎ

40

ÎÎ

100

50

ÎÎ

40

ÎÎ

160

65

ÎÎ

50

ÎÎ

Max

200

ÎÎ

100

ÎÎ

80

ÎÎ

200
100

ÎÎ

80

ÎÎ

300
130

ÎÎ

100

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

V

14

DD

PULSE

GENERATOR

INPUT

*

C

OUTPUT

L

VSS7

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to V

SS

.

INVERTING

NON–INVERTING

20 ns 20 ns

INPUT

t

PHL

OUTPUT

t

THL

t

OUTPUT

PLH

t

TLH

50%

10%

90%

90%

50%

10%

50%

10%

90%

t

PLH

t

TLH

t

PHL

t

THL

Î

Unit

ns

Î

Î

ns

Î

Î

ns

Î

Î

V
0 V

V
V

V
V

DD

OH

OL

OH

OL

Figure 1. Switching Time Test Circuit and Waveforms

CIRCUIT SCHEMATIC

MC14012B

One of Two Gates Shown

V

DD

14

2, 9

3, 10

4, 11

5, 12

V

SS

SAME AS

ABOVE

*Inverter omitted

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3

*

7

V

DD

1, 13

V

SS

MC14012B

DRA

N

CURR

NT

A

DRA

N

CURR

NT

A

DRA

N

CURR

NT

A

TYPICAL B–SERIES GATE CHARACTERISTICS

)
(m
E

I

I ,

)
(m
E

I

I ,

N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURRENT (SOURCE)

DRAIN CURRENT (mA)

D

I ,

– 10

– 9.0
– 8.0
– 7.0
– 6.0
– 5.0
– 4.0

– 3.0
– 2.0

– 1.0

TA = – 55°C

– 40°C

+ 85°C

0

0

– 1.0 – 3.0 – 5.0– 4.0– 2.0

+ 25°C

+ 125°C

5.0

4.0

3.0

2.0

D

1.0

0

1.0 3.0 5.04.02.00
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

TA = – 55°C

+ 85°C

– 40°C

+ 25°C

+ 125°C

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

20
18
16
14
12
10

8.0

6.0

D

4.0

2.0
0

V

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

DS

5.03.01.0 108.06.04.02.00

TA = – 55°C

– 40°C
+ 25°C

+ 85°C
+ 125°C

9.07.0 – 5.0– 3.0– 1.0 – 10– 8.0– 6.0– 4.0– 2.0 – 9.0– 7.0

DRAIN CURRENT (mA)

D

I ,

– 50
– 45
– 40
– 35
– 30
– 25
– 20
– 15
– 10

– 5.0

TA = – 55°C

+ 25°C

0

0

, DRAIN–TO–SOURCE VOLTAGE (Vdc)

V

DS

– 40°C

+ 85°C

+ 125°C

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

)
(m
E

I

I ,

50
45
40
35
30

25
20

15

D

10

5.0
0

0

, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

V

DS

TA = – 55°C

– 40°C

+ 25°C

+ 85°C

+ 125°C

106.02.0 2016128.04.0 1814

– 100

DRAIN CURRENT (mA)

D

I ,

– 90
– 80
– 70
– 60
– 50
– 40
– 30
– 20
– 10

TA = – 55°C

– 40°C

+ 25°C

+ 85°C

+ 125°C

0

0

– 10– 6.0– 2.0 – 20– 16– 12– 8.0– 4.0 – 18– 14

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

These typical curves are not guarantees, but are design aids.

Caution: The maximum rating for output current is 10 mA per pin.

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4

MC14012B

1

TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

5.0

4.0

3.0

OUTPUT VOLTAGE (Vdc)

2.0

out

V ,

1.0

OUTPUT VOLTAGE (Vdc)

out

V ,

8.0

6.0

4.0

2.0

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

0

1.0 3.0 5.04.02.00
V

, INPUT VOLTAGE (Vdc)

in

OUTPUT VOLTAGE (Vdc)

out

V ,

8.0

6.0

4.0

2.0

10

0

0

2.0 6.0 108.04.0

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

, INPUT VOLTAGE (Vdc)

V

in

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

6
14
12
10

SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND

The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V

DC NOISE MARGIN

and VIH for the output(s) to

IL

be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.

Guaranteed minimum noise margins for both the “1” and
“0” levels =

1.0 V with a 5.0 V supply

0

0

2.0 6.0 108.04.0
, INPUT VOLTAGE (Vdc)

V

in

Figure 10. VDD = 15 Vdc

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

V

V

out

DD

V

O

V

O

0

V

IL

V

V

DD

V

in

IH

VSS = 0 VOLTS DC

V

V

out

DD

V

O

V

O

V

DD

0

V

IL

V

V

in

IH

(a) Inverting Function (b) Non–Inverting Function

Figure 11. DC Noise Immunity

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5

MC14012B

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

14 8

B

17

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–T–

SEATING
PLANE

–T–

SEATING
PLANE

N

HG

–A–

14 8

G

D 14 PL

0.25 (0.010) A

A

F

L

C

D

14 PL

0.13 (0.005)

K

J

M

M

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L

0.290 0.310 7.37 7.87

M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES

__

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

–B–

P

7 PL

M

71

0.25 (0.010) B

C

R X 45

K

M

S

B

T

S

M

_

M

F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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6

14 8

1

Z

D

e

b

0.13 (0.005)

M

E

7

A

0.10 (0.004)

H

A

1

MC14012B

P ACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

L

E

E

VIEW P

_

M

L
DETAIL P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

0.50
L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 1.42 ––– 0.056

Z

INCHES

10

_

10

0

_

_

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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