Page 1
MOTOROLA CMOS LOGIC DATA
31
MC14007UB
The MC14007UB multi–purpose device consists of three N–channel and
three P–channel enhancement mode devices packaged to provide access to
each device. These versatile parts are useful in inverter circuits, pulse–
shapers, linear amplifiers, high input impedance amplifiers, threshold
detectors, transmission gating, and functional gating.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4007A or CD4007UB
• This device has 2 outputs without ESD Protection. Anti–static
precautions must be taken.
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, l
out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Figure 1. Typical Application: 2–Input Analog Multiplexer
A
B
C
INPUT
INPUT
A
B
C
12
1
3
5
9
2
4
11
10
14
V
DD
6
7 V
SS
8
13
INPUT
1
0
OUTPUT CONDITION
A = C, B = OPEN
A = B, C = OPEN
Substrates of P–channel devices internally
connected to VDD; substrates of N–channel
devices internally connected to VSS.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXUBCP Plastic
MC14XXXUBCL Ceramic
MC14XXXUBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
11
12
13
14
8
9
105
4
3
2
1
7
6
GATE
C
S–P
C
OUT
C
D–P
A
V
DD
D–N
A
S–N
C
S–N
B
GATE
B
S–P
B
D–P
B
V
SS
GATE
A
D–N
B
PIN ASSIGNMENT
D = DRAIN
S = SOURCE
SCHEMATIC
14 13 2 1 11
126
7 8 3 4 5 10 9
VDD = PIN 14
VSS = PIN 7
Page 2
MOTOROLA CMOS LOGIC DATAMC14007UB
32
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
Vin = 0 or V
DD
“1” Level
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.0
2.0
2.5
Vdc
(VO = 0.5 Vdc)
“1” Level
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
V
IH
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 5.0
– 1.0
– 2.5
– 10
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
1.0
2.5
10
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
I
T
5.0
10
15
IT = (0.7 µA/kHz) f + IDD/6
IT = (1.4 µA/kHz) f + IDD/6
IT = (2.2 µA/kHz) f + IDD/6
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
Page 3
MOTOROLA CMOS LOGIC DATA
33
MC14007UB
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
V
DD
Vdc
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Min
Typ #
Max
Unit
Output Rise Time
t
TLH
= (1.2 ns/pF) CL + 30 ns
t
TLH
= (0.5 ns/pF) CL + 20 ns
t
TLH
= (0.4 ns/pF) CL + 15 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
TLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
90
45
35
180
90
70
ns
Output Fall Time
t
THL
= (1.2 ns/pF) CL + 15 ns
t
THL
= (0.5 ns/pF) CL + 15 ns
t
THL
= (0.4 ns/pF) CL + 10 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
THL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
75
40
30
150
80
60
ns
Turn–Off Delay Time
t
PLH
= (1.5 ns/pF) CL + 35 ns
t
PLH
= (0.2 ns/pF) CL + 20 ns
t
PLH
= (0.15 ns/pF) CL + 17.5 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
60
30
25
125
75
55
ns
Turn–On Delay Time
t
PHL
= (1.0 ns/pF) CL + 10 ns
t
PHL
= (0.3 ns/pF) CL + 15 ns
t
PHL
= (0.2 ns/pF) CL + 15 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
60
30
25
125
75
55
ns
*The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics
VDD = –V
GS
VDD = V
GS
14
14
VDS = VOH – V
DD
VDS = V
OL
V
SS
VSS7
7
I
OH
I
OL
I
OH
, DRAIN CURRENT (mAdc)
I
OL
, DRAIN CURRENT (mAdc)
0
–4.0
–8.0
–12
–16
–20
–8.0–10 –6.0 –4.0 –2.0 –0
VDS, DRAIN VOLTAGE (Vdc)
20
16
12
8.0
4.0
0
0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc)
TA = –55°C
TA = +25
°
C
TA = +125
°
C
a
b
c
VGS = –5.0 Vdc b
c
a
–10 Vdc
–15 Vdc
c
b
c
b
a
a
a
b
c
a
b
c
a
b
c
5.0 Vdc
TA = –55°C
TA = +25
°
C
TA = +125
°
C
a
b
c
VGS = 15 Vdc
10 Vdc
All unused inputs connected to ground. All unused inputs connected to ground.
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
Page 4
MOTOROLA CMOS LOGIC DATAMC14007UB
34
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
500
µ
F
0.01
µ
F
CERAMIC
14
C
L
V
out
VSS7
V
in
I
D
V
in
V
out
90%
50%
10%
90%
50%
10%
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
t
THLtTLH
t
PHL
t
PLH
APPLICATIONS
The MC14007UB dual pair plus inverter, which has access
to all its elements offers a number of unique circuit applications. Figures 1, 5, and 6 are a few examples of the device
flexibility.
Figure 5. 3–State Buffer
+V
DD
DISABLE 3
INPUT 10
DISABLE
6
12 OUTPUT
11
1
2
9
8
7
INPUT DISABLE OUTPUT
1
0
X
0
0
1
0
1
OPEN
X = Don’t Care
Figure 6. AOI Functions Using Tree Logic
V
DD
14
13
11
10
3
6
B
C
A
9
5
4
8
7
1
2
OUTPUT
OUT = A+B
•
C
Substrates of P–channel devices internally connected to VDD;
Substrates of N–channel devices internally connected to VSS.
12
Page 5
MOTOROLA CMOS LOGIC DATA
35
MC14007UB
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
C
14 PLD
GF N
K
14 PLJ
M
L
S
B
M
0.25 (0.010) T
S
A
M
0.25 (0.010) T
–T–
SEATING
PLANE
1 7
14 9
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
_ _ _ _
Page 6
MOTOROLA CMOS LOGIC DATAMC14007UB
36
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P
7 PL
14 8
71
M
0.25 (0.010) B
M
S
B
M
0.25 (0.010) A
S
T
–T–
F
R
X 45
SEATING
PLANE
D 14 PL
K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14007UB/D
*MC14007UB/D*
◊
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