Datasheet MC14001UBCP, MC14001UBD, MC14001UBDR2 Datasheet (MOTOROLA)

MC14001UB, MC14011UB

UB-Suffix Series CMOS Gates

The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non–buffered functions.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linear and Oscillator Applications

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

• Double Diode Protection on All Inputs

• Pin–for–Pin Replacements for Corresponding CD4000 Series UB

Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C Lead Temperature

L

SS

or VDD). Unused outputs must be left open.

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 2.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

should be constrained

out

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MC14001UB

Quad 2–Input NOR Gate

MC14011UB

Quad 2–Input NAND Gate

MARKING

DIAGRAMS

14

PDIP–14

P SUFFIX

CASE 646

SOIC–14

D SUFFIX

CASE 751A

XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

ORDERING INFORMATION

Device Package Shipping

MC14001UBCP PDIP–14 2000/Box MC14001UBD SOIC–14 MC14001UBDR2 SOIC–14 2500/Tape & Reel MC1401 1UBCP PDIP–14 MC1401 1UBD SOIC–14 MC1401 1UBDR2 SOIC–14

MC140XXUBCP

AWLYYWW

1

14

140XXU

AWLYWW

1

55/Rail

2000/Box

55/Rail

2500/Tape & Reel

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14001UB/D

MC14001UB, MC14011UB

LOGIC DIAGRAMS

MC14001UB

Quad 2–Input

NOR Gate

1 2 5 6 8

9 12 13

MC14001UB

Quad 2–Input NOR Gate

IN 1 IN 2

OUT

IN 1 IN 2

1

A

2

A

3

A

4

B B

6

B

7

V

SS

14

V

DD

13

IN 2

12

IN 1

11

OUT OUT

105

9

IN 2

8

IN 1

3

4

10

11

VDD = PIN 14

V

= PIN 7

SS

FOR ALL DEVICES

PIN ASSIGNMENTS

D D

D C

C C

MC14011UB

Quad 2–Input

NAND Gate

1 2

5 6

8 9

12 13

3

4

10

11

MC14011UB

Quad 2–Input NAND Gate

1

IN 1

IN 2 OUT OUT

IN 1

IN 2

A

2

A

3

A

4

B B

6

B

7

V

SS

14 13 12 11 105

9 8

V

DD

IN 2 IN 1 OUT OUT IN 2

IN 1

D D

D C

C C

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2

MC14001UB, MC14011UB

V

DD

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Output Voltage “0” Level

V

= VDD or 0

in

ОООООООО

Vin = 0 or V

ОООООООО

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

(VO = 0.5 Vdc) “1” Level

ОООООООО

(V

O

(V

O

ОООООООО

DD

= 4.5 Vdc) = 9.0 Vdc) = 13.5 Vdc)

= 1.0 Vdc) = 1.5 Vdc)

“1” Level

Output Drive Current

(V

= 2.5 Vdc) Source

OH

ОООООООО

(V

= 4.6 Vdc)

OH

(V

= 9.5 Vdc)

OH

ОООООООО

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink

ОООООООО

(V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

ОООООООО

Input Current Input Capacitance

(V

= 0)

in

Quiescent Current

ОООООООО

(Per Package)

ОООООООО

Total Supply Current

(4.) (5.)

(Dynamic plus Quiescent,

ОООООООО

Per Gate C

= 50 pF)

L

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

ÎÎ

I

IH

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

I

DD

ÎÎ

I

ÎÎ

Vdc

Min

5.0 10

Î

15

5.0 10

Î

15

IL

Î

5.0 10

Î

4.95

9.95

Î

14.95

Î

15

5.0

Î

10 15

Î

5.0

Î

5.0 10

Î

15

5.0

Î

10 15

Î

4.0

Î

8.0

12.5

Î

– 1.2

Î

– 0.25 – 0.62

Î

– 1.8

0.64

Î

1.6

4.2

Î

15

in

—

5.0

Î

10 15

Î

T

5.0

Î

10

Î

15

ООООООООООООООО

– 55_C

— — —

— —

— — —

SS

)

Max

0.05

Î

0.05

Î

± 0.1

0.25

Î

— — —

1.0

2.0

2.5 —

— —

— — — —

— — —

—

0.5

1.0

25_C

Min

— —

ÎÎ

—

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

4.0

ÎÎ

8.0

12.5

ÎÎ

– 1.0

ÎÎ

– 0.2 – 0.5

ÎÎ

– 1.5

0.51

ÎÎ

1.3

3.4

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

(3.)

Typ

0 0

ÎÎ

0

5.0 10

ÎÎ

15

ÎÎ

2.25

4.50

ÎÎ

6.75

2.75

ÎÎ

5.50

8.25

ÎÎ

– 1.7

ÎÎ

– 0.36

– 0.9

ÎÎ

– 3.5

0.88

ÎÎ

2.25

8.8

ÎÎ

±0.00001

5.0

0.0005

ÎÎ

0.0010

0.0015

ÎÎ

IT = (0.3 µA/kHz) f + IDD/N I

= (0.6 µA/kHz) f + IDD/N

T

I

= (0.8 µA/kHz) f + IDD/N

T

Max

0.05

Î

0.05 —

—

Î

—

Î

1.0

2.0

Î

2.5 —

Î

— —

Î

—

Î

— —

Î

— —

Î

— —

Î

± 0.1

7.5

0.25

Î

0.5

1.0

Î

Min

— —

Î

—

4.95

9.95

Î

14.95

Î

— —

Î

—

4.0

Î

8.0

12.5

Î

– 0.7

Î

– 0.14 – 0.35

Î

– 1.1

0.36

Î

0.9

2.4

Î

— —

—

Î

— —

Î

125_C

Î

± 1.0

Î

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

T

per package.

Max

0.05

0.05 —

— —

1.0

2.0

2.5 —

— —

— — — —

— — —

—

7.5 15 30

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

µAdc

pF

µAdc

Î

µAdc

Î

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3

MC14001UB, MC14011UB

Î

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(6.)

(C

L

= 50 pF, T

Output Rise Time

t

= (3.0 ns/pF) CL + 30 ns

TLH

= (1.5 ns/pF) CL + 15 ns

t

ООООООООООООО

TLH

t

= (1.1 ns/pF) CL + 10 ns

TLH

Output Fall Time

ООООООООООООО

t

= (1.5 ns/pF) CL + 25 ns

THL

= (0.75 ns/pF) CL + 12.5 ns

t

ООООООООООООО

THL

t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time

ООООООООООООО

t

, t

PLH

t

PLH

ООООООООООООО

t

PLH

= (1.7 ns/pF) CL + 30 ns

PHL

, t

= (0.66 ns/pF) CL + 22 ns

PHL

, t

= (0.50 ns/pF) CL + 15 ns

PHL

= 25_C)

A

Symbol

ÎÎÎ

t

TLH

ÎÎÎ

t

THL

ÎÎÎ

t

, t

PLH

ÎÎÎ

PHL

V

DD

Vdc

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0 10

ÎÎ

15

Min

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

(7.)

Typ

ÎÎ

180

90

ÎÎ

65

ÎÎ

100

50

ÎÎ

40

ÎÎ

90 50

ÎÎ

40

Max

ÎÎ

360 180

ÎÎ

130

ÎÎ

200 100

ÎÎ

80

ÎÎ

180 100

ÎÎ

80

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns

V

DD

14

PULSE

INPUT

GENERATOR

*

V

7

SS

*All unused inputs of AND, NAND gates must be

connected to V

DD

.

OUTPUT

C

L

INPUT

t

PHL

OUTPUT

INVERTING

90% 50% 10%

t

THL

90% 50%

10%

t

TLH

All unused inputs of OR, NOR gates must be connected to V

SS

.

Figure 1. Switching Time Test Circuit and Waveforms

t

PLH

Unit

Î

ns

Î

ns

Î

ns

Î

V

0 V V

V

DD

OH

OL

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4

MC14001UB, MC14011UB

MC14001UB CIRCUIT SCHEMATIC

MC14011UB CIRCUIT SCHEMATIC

(1/4 of Device Shown)

V

DD

14 103

1

2

8

9

14 V

DD

3, 4, 10, 11

1, 6, 8, 13

2, 5, 9, 12

10 Vdc

13

12

8.0

6.0

4.0

2.0 0

, DRAIN CURRENT (mAdc)

D

I

16 14 12 10

8.0

6.0

, OUTPUT VOLTAGE (Vdc)

4.0

out

V

2.0 0

VDD = 15 Vdc

10 Vdc

a

b

Unused input connected to V

SS

TA = +125°C

a

T

b

5.0 Vdc

a

b

0 2.0 4.0 6.0 8.0 10 12 14 16

V

, INPUT VOLTAGE (Vdc)

in

.

= –55°C

A

7 V

SS

Figure 3. T ypical Voltage Transfer

Characteristics versus

6

5

4711

V

SS

16 14

VDD = 15 Vdc

TA = +25°C Unused input connected to

12

10 Vdc

10

V

.

SS

a

One input only

b

Both inputs

8.0 a

6.0

5.0 Vdc

, OUTPUT VOLTAGE (Vdc)

4.0

out

V

b

2.0

0

0 2.0 4.0 6.0 8.0 10 12 14 16

b

a

b

15 Vdc

a

Vin, INPUT VOLTAGE (Vdc)

Figure 2. T ypical Voltage and

Current Transfer Characteristics

T emperature

0

TA = –55°C T

= +25°C

A

T

= +125°C

A

–10 Vdc

VGS = –5.0 Vdc

c

V

, DRAIN VOLTAGE (Vdc)

DS

–2.0

a b

–4.0

c

–6.0

, DRAIN CURRENT (mAdc)

D

I

–8.0

–10

–10 –8.0 –6.0 –4.0 –2.0 0

c b

a

b

c

b

a a

Figure 4. T ypical Output Source

Characteristics

10

8.0

6.0

4.0

, DRAIN CURRENT (mAdc)

D

–15 Vdc

I

2.0

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5

a

c

b

15 Vdc

a

b

VGS = 10 Vdc

c

a

TA = –55°C

= +25°C

b

T

A

T

= +125°C

c

A

a

bc5.0 Vdc

0

2.0 4.0 6.0 8.0 10 V

, DRAIN VOLTAGE (Vdc)

DS

Figure 5. T ypical Output Sink

Characteristics

MC14001UB, MC14011UB

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

14 8

B

17

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–T–

SEATING PLANE

N

HG

A F

L

C

D

14 PL

0.13 (0.005)

K

J

M

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M ––– 10 ––– 10 N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES

__

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6

–T–

SEATING PLANE

–A–

14 8

G

D 14 PL

0.25 (0.010) A

MC14001UB, MC14011UB

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

–B–

P

7 PL

M

71

0.25 (0.010) B

C

X 45

R

K

M

S

B

T

S

M

_

M

F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

____

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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MC14001UB, MC14011UB

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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MC14001UB/D

Datasheet MC14001UBCP, MC14001UBD, MC14001UBDR2 Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual