Page 1
MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low-power TTL Loads or One Low-power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
• Pin-for-Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
DD
Vin, V
Iin, I
P
T
T
stg
T
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
DC Supply Voltage Range - 0.5 to +18.0 V
Input or Output Voltage Range
out
out
D
A
L
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 2)
Ambient Temperature Range - 55 to +125 °C
Storage Temperature Range - 65 to +150 °C
Lead Temperature
(8-Second Soldering)
) (Note 1)
SS
- 0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
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MARKING
DIAGRAMS
14
PDIP-14
P SUFFIX
CASE 646
SOIC-14
D SUFFIX
CASE 751A
TSSOP-14
DT SUFFIX
CASE 948G
SOEIAJ-14
F SUFFIX
CASE 965
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC140xxBCP
AWLYYWW
1
14
140xxB
AWLYWW
1
14
1
14
MC140xxB
AWLYWW
1
DEVICE INFORMATION
Device Description
MC14001B Quad 2-Input NOR Gate
14
0xxB
ALYW
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
Semiconductor Components Industries, LLC, 2003
March, 2003 - Rev. 3
(Vin or V
SS
or VDD). Unused outputs must be left open.
) VDD.
out
and V
in
should be constrained
out
1 Publication Order Number:
MC14011B Quad 2-Input NAND Gate
MC14023B Triple 3-Input NAND Gate
MC14025B Triple 3-Input NOR Gate
MC14071B Quad 2-Input OR Gate
MC14073B Triple 3-Input AND Gate
MC14081B Quad 2-Input AND Gate
MC14082B Dual 4-Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
MC14001B/D
Page 2
MC14001B Series
LOGIC DIAGRAMS
NOR
MC14001B
Quad 2-Input NOR Gate
1
2
5
6
2 INPUT
8
9
12
13
MC14025B
Triple 3-Input NOR Gate
1
2
8
3
4
5
3 INPUT
11
12
13
NAND
MC14011B
Quad 2-Input NAND Gate
3
4
10
11
1
2
5
6
8
9
12
13
3
4
10
11
Quad 2-Input OR Gate
1
2
5
6
8
9
12
13
MC14023B
Triple 3-Input NAND Gate
1
9
6
10
2
9
8
3
4
6
5
11
12
10
13
Triple 3-Input AND Gate
1
2
8
3
4
5
11
12
13
OR
MC14071B
MC14073B
AND
MC14081B
Quad 2-Input AND Gate
3
4
10
11
1
2
5
6
8
9
12
13
3
4
10
11
MC14082B
Dual 4-Input AND Gate
9
6
10
2
3
4
1
5
9
10
11
12
NC = 6, 8
13
VDD = PIN 14
V
= PIN 7
SS
FOR ALL DEVICES
MC14001B
Quad 2-Input NOR Gate
IN 1
IN 2
OUT
OUT
IN 1
IN 2
V
1
A
2
A
3
A
4
B
B
6
B
7
SS
14
V
DD
13
IN 2
12
IN 1
11
OUT
OUT
105
9
IN 2
8
IN 1
MC14071B
Quad 2-Input OR Gate
IN 1
IN 2
OUT
OUT
IN 1
IN 2
V
1
A
2
A
3
A
4
B
B
6
B
7
SS
14
V
DD
13
IN 2
12
IN 1
11
OUT
OUT
105
9
IN 2
8
IN 1
MC14011B
Quad 2-Input NAND Gate
1
IN 1
A
2
D
D
C
C
IN 2
A
3
OUT
A
4
OUT
D
C
IN 1
IN 2
B
B
6
B
7
V
SS
MC14073B
Triple 3-Input AND Gate
1
IN 1
A
2
D
D
C
C
IN 2
A
3
IN 1
B
4
IN 2
D
C
IN 3
OUT
B
B
6
B
7
V
SS
PIN ASSIGNMENTS
Triple 3-Input NAND Gate
14
V
DD
13
IN 2
D
12
IN 1
D
11
OUT
D
OUT
105
14
13
12
11
105
C
9
IN 2
C
8
IN 1
C
V
DD
IN 3
C
IN 2
C
IN 1
C
OUT
C
9
OUT
A
8
IN 3
A
IN 1
A
IN 2
A
IN 1
B
IN 2
B
IN 3
B
OUT
B
V
SS
Quad 2-Input AND Gate
IN 1
A
IN 2
A
OUT
A
OUT
B
IN 1
B
IN 2
B
V
SS
MC14023B
1
2
3
4
6
7
MC14081B
1
2
3
4
6
7
MC14025B
Triple 3-Input NOR Gate
1
14
V
DD
13
IN 3
C
12
IN 2
C
11
IN 1
C
OUT
105
C
9
OUT
A
8
IN 3
A
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
A
2
A
3
B
4
B
B
6
B
7
V
SS
14
V
DD
13
IN 3
C
12
IN 2
C
11
IN 1
C
OUT
105
C
9
OUT
A
8
IN 3
A
MC14082B
Dual 4-Input AND Gate
1
14
V
DD
13
IN 2
D
12
IN 1
D
11
OUT
D
OUT
105
C
9
IN 2
C
8
IN 1
C
OUT
IN 1
IN 2
IN 3
IN 4
A
2
A
3
A
4
A
A
6
NC
7
V
SS
14
V
DD
13
OUT
B
12
IN 4
B
11
IN 3
B
IN 2
105
B
9
IN 1
B
8
NC
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2
NC = NO CONNECTION
Page 3
MC14001B Series
V
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
DD
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Min
—
—
Î
—
4.95
9.95
Î
14.95
Î
—
—
Î
—
Î
3.5
7.0
Î
11
Î
– 3.0
– 0.64
Î
– 1.6
Î
– 4.2
0.64
1.6
Î
4.2
—
—
Î
—
—
Î
—
ООООООООООООООО
ООООООООООООООО
Characteristic
Output Voltage “0” Level
V
= VDD or 0
in
ОООООООО
“1” Level
V
= 0 or V
ОООООООО
in
Input Voltage “0” Level
ОООООООО
(V
O
(V
ОООООООО
O
(V
O
ОООООООО
(V
O
(V
O
ОООООООО
(V
O
Output Drive Current
ОООООООО
(V
OH
(V
OH
ОООООООО
(V
OH
ОООООООО
(V
OH
DD
= 4.5 or 0.5 Vdc)
= 9.0 or 1.0 Vdc)
= 13.5 or 1.5 Vdc)
“1” Level
= 0.5 or 4.5 Vdc)
= 1.0 or 9.0 Vdc)
= 1.5 or 13.5 Vdc)
= 2.5 Vdc) Source
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
ОООООООО
(V
= 1.5 Vdc)
OL
Input Current
Input Capacitance
ОООООООО
(V
= 0)
in
Quiescent Current
(Per Package)
ОООООООО
Total Supply Current
ОООООООО
(Dynamic plus Quiescent,
Per Gate, C
ОООООООО
(4) (5)
= 50 pF)
L
Symbol
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
ÎÎ
I
OL
ÎÎ
I
in
C
in
ÎÎ
I
DD
ÎÎ
I
T
ÎÎ
ÎÎ
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
5.0
10
15
5.0
10
15
15
—
5.0
10
15
5.0
10
15
SS
- 55C
)
Max
0.05
0.05
Î
0.05
—
—
Î
—
Î
1.5
3.0
Î
4.0
Î
—
—
Î
—
Î
—
—
Î
—
Î
—
—
—
Î
—
± 0.1
—
Î
0.25
0.5
Î
1.0
25C
Min
—
—
ÎÎ
—
4.95
9.95
ÎÎ
14.95
ÎÎ
—
—
ÎÎ
—
ÎÎ
3.5
7.0
ÎÎ
11
ÎÎ
– 2.4
– 0.51
ÎÎ
– 1.3
ÎÎ
– 3.4
0.51
1.3
ÎÎ
3.4
—
—
ÎÎ
—
—
ÎÎ
—
(3)
Typ
0
0
Î
0
5.0
10
Î
15
Î
2.25
4.50
Î
6.75
Î
2.75
5.50
Î
8.25
Î
– 4.2
– 0.88
Î
– 2.25
Î
– 8.8
0.88
2.25
Î
8.8
±0.00001
5.0
Î
0.0005
0.0010
Î
0.0015
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
IT = (0.3 µA/kHz) f + IDD/N
I
= (0.6 µA/kHz) f + IDD/N
T
= (0.9 µA/kHz) f + IDD/N
I
T
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
± 0.1
7.5
0.25
0.5
1.0
Min
—
—
Î
—
4.95
9.95
Î
14.95
Î
—
—
Î
—
Î
3.5
7.0
Î
11
Î
– 1.7
– 0.36
Î
– 0.9
Î
– 2.4
0.36
0.9
Î
2.4
—
—
Î
—
—
Î
—
125C
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
Î
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25C.
5. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL - 50) Vfk
I
T(CL
where: I
is in µA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
per package.
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
7.5
15
30
Unit
Vdc
Î
Vdc
Î
Vdc
Î
Î
Vdc
Î
Î
mAdc
Î
Î
Î
mAdc
Î
µAdc
pF
Î
µAdc
Î
µAdc
Î
Î
http://onsemi.com
3
Page 4
MC14001B Series
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
B-SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS
ООООООООООООО
Characteristic
(6)
(CL = 50 pF, T
Output Rise Time, All B-Series Gates
t
= (1.35 ns/pF) CL + 33 ns
TLH
ООООООООООООО
t
= (0.60 ns/pF) CL + 20 ns
TLH
ООООООООООООО
= (0.40 ns/PF) CL + 20 ns
t
TLH
Output Fall Time, All B-Series Gates
t
= (1.35 ns/pF) CL + 33 ns
ООООООООООООО
THL
= (0.60 ns/pF) CL + 20 ns
t
THL
ООООООООООООО
t
= (0.40 ns/pF) CL + 20 ns
THL
Propagation Delay Time
ООООООООООООО
MC14001B, MC14011B only
, t
t
PLH
ООООООООООООО
t
PLH
ООООООООООООО
t
PLH
All Other 2, 3, and 4 Input Gates
ООООООООООООО
t
PLH
t
ООООООООООООО
PLH
t
PLH
ООООООООООООО
8-Input Gates (MC14068B, MC14078B)
t
ООООООООООООО
PLH
t
PLH
ООООООООООООО
t
PLH
= (0.90 ns/pF) CL + 80 ns
PHL
, t
= (0.36 ns/pF) CL + 32 ns
PHL
, t
= (0.26 ns/pF) CL + 27 ns
PHL
, t
= (0.90 ns/pF) CL + 115 ns
PHL
, t
= (0.36 ns/pF) CL + 47 ns
PHL
, t
= (0.26 ns/pF) CL + 37 ns
PHL
, t
= (0.90 ns/pF) CL + 155 ns
PHL
, t
= (0.36 ns/pF) CL + 62 ns
PHL
, t
= (0.26 ns/pF) CL + 47 ns
PHL
= 25C)
A
ÎÎÎ
Symbol
t
TLH
ÎÎÎ
ÎÎÎ
t
THL
ÎÎÎ
ÎÎÎ
t
PLH
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
DD
ÎÎ
Vdc
5.0
ÎÎ
10
ÎÎ
15
ÎÎ
5.0
10
ÎÎ
15
, t
PHL
ÎÎ
5.0
ÎÎ
10
ÎÎ
15
ÎÎ
5.0
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
ÎÎ
15
ÎÎ
Min
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
(7)
Typ
100
ÎÎ
50
ÎÎ
40
ÎÎ
100
50
ÎÎ
40
ÎÎ
125
ÎÎ
50
ÎÎ
40
ÎÎ
160
65
ÎÎ
50
ÎÎ
200
ÎÎ
80
ÎÎ
60
ÎÎ
Max
200
ÎÎ
100
ÎÎ
80
ÎÎ
200
100
ÎÎ
80
ÎÎ
250
ÎÎ
100
ÎÎ
80
ÎÎ
300
130
ÎÎ
100
ÎÎ
350
ÎÎ
150
ÎÎ
110
6. The formulas given are for the typical characteristics only at 25C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Î
Unit
ns
Î
Î
ns
Î
Î
ns
Î
Î
Î
Î
Î
Î
Î
Î
V
14
DD
PULSE
INPUT
GENERATOR
*
C
L
VSS7
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to V
Figure 1. Switching Time Test Circuit and Waveforms
OUTPUT
.
SS
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4
20 ns 20 ns
INPUT
OUTPUT
INVERTING
OUTPUT
NON−INVERTING
t
PHL
t
t
THL
PLH
V
0 V
V
V
V
V
DD
OH
OL
OH
OL
90%
50%
10%
90%
t
TLH
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
PHL
t
THL
Page 5
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
1, 6, 8, 13
2, 5, 9, 12
MC14001B, MC14071B
One of Four Gates Shown
V
DD
*
V
SS
*Inverter omitted in MC14001B
MC14025B
One of Three Gates Shown
V
14
V
DD
1, 3, 11
2, 4, 12
3, 4, 10, 11
V
7
SS
8, 5, 13
DD
14
V
DD
*
V
SS
V
DD
V
SS
*Inverter omitted in MC14025B
9, 6, 10
7
V
SS
2, 4, 12
1, 3, 11
8, 5, 13
MC14023B, MC14073B
One of Three Gates Shown
V
DD
V
SS
V
DD
V
SS
*Inverter omitted in MC14023B
CIRCUIT SCHEMATIC
NAND, AND GATES
14
V
DD
*
V
7
SS
2, 5, 9, 12
1, 6, 8, 13
9, 6, 10
MC14011B, MC14081B
One of Four Gates Shown
14
*
*Inverter omitted in MC14011B
7
V
DD
3, 4, 10, 11
V
SS
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5
Page 6
5.0
4.0
3.0
2.0
DRAIN CURRENT (mA)
D
I ,
1.0
MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS
N-CHANNEL DRAIN CURRENT (SINK) P-CHANNEL DRAIN CURRENT (SOURCE)
− 10
− 9.0
− 8.0
T
= − 55°C
A
− 40°C
+ 25°C
+ 85°C
+ 125°C
0
1.0 3.0 5.04.02.00
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc Figure 3. VGS = - 5.0 Vdc
− 7.0
− 6.0
− 5.0
− 4.0
DRAIN CURRENT (mA)
− 3.0
D
I ,
− 2.0
− 1.0
0
0
− 1.0 − 3.0 − 5.0− 4.0− 2.0
T
= − 55°C
A
+ 85°C
− 40°C
+ 25°C
+ 125°C
8.0
DRAIN CURRENT (mA)
6.0
D
I ,
4.0
2.0
DRAIN CURRENT (mA)
D
I ,
5.0
20
18
16
14
12
10
T
= − 55°C
A
− 40°C
+ 25°C
+ 85°C
+ 125°C
DRAIN CURRENT (mA)
D
I ,
− 50
− 45
− 40
− 35
− 30
− 25
− 20
− 15
− 10
T
= − 55°C
A
+ 25°C
− 40°C
+ 85°C
+ 125°C
− 5.0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
5.03.01.0 108.06.04.02.00
9.07.0 − 5.0− 3.0− 1.0 − 10− 8.0− 6.0− 4.0− 2.0 − 9.0− 7.0
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
Figure 4. VGS = 10 Vdc Figure 5. VGS = - 10 Vdc
50
45
40
35
30
25
20
15
T
= − 55°C
A
− 40°C
+ 25°C
+ 85°C
+ 125°C
10
0
0
, DRAIN−TO−SOURCE VOLTAGE (Vdc) VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
106.02.0 2016128.04.0 1814
− 100
DRAIN CURRENT (mA)
D
I ,
− 90
− 80
− 70
− 60
− 50
− 40
− 30
− 20
− 10
T
= − 55°C
A
− 40°C
+ 25°C
+ 85°C
+ 125°C
0
0
− 10− 6.0− 2.0 − 20− 16− 12− 8.0− 4.0 − 18− 14
Figure 6. VGS = 15 Vdc Figure 7. VGS = - 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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Page 7
MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
5.0
4.0
3.0
OUTPUT VOLTAGE (Vdc)
2.0
out
V ,
1.0
0
16
14
12
10
8.0
6.0
OUTPUT VOLTAGE (Vdc)
4.0
out
V ,
2.0
0
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
1.0 3.0 5.04.02.00
, INPUT VOLTAGE (Vdc)
V
in
Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc
2.0 6.0 108.04.0
, INPUT VOLTAGE (Vdc)
V
in
Figure 10. VDD = 15 Vdc
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
10
8.0
6.0
OUTPUT VOLTAGE (Vdc)
4.0
out
V ,
2.0
0
0
2.0 6.0 108.04.0
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
, INPUT VOLTAGE (Vdc)
V
in
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V
and VIH for the output(s) to
IL
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
V
V
out
DD
V
O
V
O
V
DD
0
V
IL
V
V
in
IH
VSS = 0 VOLTS DC
V
V
out
DD
V
O
V
O
0
V
IL
(a) Inverting Function (b) Non-Inverting Function
Figure 11. DC Noise Immunity
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7
V
DD
V
in
V
IH
Page 8
MC14001B Series
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646-06
ISSUE M
14 8
B
17
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
-T-
SEATING
PLANE
-T-
SEATING
PLANE
N
HG
-A-
14 8
G
D 14 PL
0.25 (0.010) A
A
F
L
C
D
14 PL
0.13 (0.005)
K
J
M
M
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
0.290 0.310 7.37 7.87
M −−− 10 −−− 10
N 0.015 0.039 0.38 1.01
MILLIMETERSINCHES
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A-03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
-B-
71
M
7 PL
P
M
0.25 (0.010) B
X 45
C
R
K
S
B
T
S
M
M
F
J
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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Page 9
MC14001B Series
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G-01
ISSUE O
0.10 (0.004)
-T-
SEATING
PLANE
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
-V-
B
-U-
N
F
7
DETAIL E
K
K1
J
J1
SECTION N-N
C
D
G
H
DETAIL E
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
-W-
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
INCHESMILLIMETERS
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9
Page 10
14 8
1
Z
D
e
b
0.13 (0.005)
M
E
7
A
0.10 (0.004)
H
A
1
MC14001B Series
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965-01
ISSUE O
L
E
E
VIEW P
M
L
DETAIL P
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
Q
1
c
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
0.50
L
1.10 1.50 0.043 0.059
E
0
M
Q
0.70 0.90 0.028 0.035
1
−−− 1.42 −−− 0.056
Z
INCHES
10
10
0
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Page 11
MC14001B Series
ORDERING & SHIPPING INFORMATION:
Device Package Shipping
MC14001BCP PDIP-14 2000 Units per Box
MC14001BD SOIC-14 2750 Units per Box
MC14001BDR2 SOIC-14 2500 Units / Tape & Reel
MC14001BDT TSSOP-14 96 Units per Rail
MC14001BDTR2 TSSOP-14 2500 Units / Tape & Reel
MC14011BCP PDIP-14 2000 Units per Box
MC14011BD SOIC-14 2750 Units per Box
MC14011BDR2 SOIC-14 2500 Units / Tape & Reel
MC14011BDT TSSOP-14 96 Units per Rail
MC14011BDTEL TSSOP-14 2000 Units / Tape & Reel
MC14011BDTR2 TSSOP-14 2500 Units / Tape & Reel
MC14023BCP PDIP-14 2000 Units per Box
MC14023BD SOIC-14 2750 Units per Box
MC14023BDR2 SOIC-14 2500 Units / Tape & Reel
MC14025BCP PDIP-14 2000 Units per Box
MC14025BD SOIC-14 2750 Units per Box
MC14025BDR2 SOIC-14 2500 Units / Tape & Reel
ORDERING & SHIPPING INFORMATION:
Device Package Shipping
MC14071BCP PDIP-14 2000 Units per Box
MC14071BD SOIC-14 55 Units per Rail
MC14071BDR2 SOIC-14 2500 Units / Tape & Reel
MC14071BDT TSSOP-14 96 Units per Rail
MC14071BDTR2 TSSOP-14 2500 Units / Tape & Reel
MC14073BCP PDIP-14 2000 Units per Box
MC14073BD SOIC-14 55 Units per Rail
MC14073BDR2 SOIC-14 2500 Units / Tape & Reel
MC14081BCP PDIP-14 2000 Units per Box
MC14081BD SOIC-14 55 Units per Rail
MC14081BDR2 SOIC-14 2500 Units / Tape & Reel
MC14081BDT TSSOP-14 96 Units per Rail
MC14081BDTR2 TSSOP-14 2500 Units / Tape & Reel
MC14082BCP PDIP-14 2000 Units per Box
MC14082BD SOIC-14 55 Units per Rail
MC14082BDR2 SOIC-14 2500 Units / Tape & Reel
For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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11
Page 12
MC14001B Series
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
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PUBLICATION ORDERING INFORMATION
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Phone: 81-3-5773-3850
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For additional information, please contact your local
Sales Representative.
MC14001B/D
12
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