Datasheet MC14000UBCL, MC14000UBCP, MC14000UBD Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATAMC14000UB

2

   
 

The MC14000UB dual 3–input NOR gate plus inverter is constructed with
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find primary
use where low power dissipation and/or high noise immunity is desired.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Swing Independent of Fanout

• Pin–for–Pin Replacement for CD4000UB

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

lin, l

out

Input or Output Current (DC or Transient),
per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

CIRCUIT SCHEMATIC

14 11 12 13 8

67 10

V

SS

9

3

4

5

V

DD



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94

LOGIC DIAGRAM



L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXUBCP Plastic
MC14XXXUBCL Ceramic
MC14XXXUBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT

B

IN 1

B

IN 2

B

IN 3

B

V

DD

IN 1

C

OUT

C

IN 2

A

IN 1

A

NC

NC

V

SS

OUT

A

IN 3

A

NC = NO CONNECTION

3
4
5

6

11
12
13

10

8 9

VDD = PIN 14

VSS = PIN 7

MOTOROLA CMOS LOGIC DATA

3

MC14000UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

+ 125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

ÎÎÎ

ÎÎÎ

Max

Unit

Output Voltage “0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

Vdc

Input Voltage “0” Level

(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.0

2.0

2.5

—
—
—

2.25

4.50

6.75

1.0

2.0

2.5

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

1.0

2.0

2.5

Vdc

“1” Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

V

IH

5.0
10
15

4.0

8.0

12.5

—
—
—

4.0

8.0

12.5

2.75

5.50

8.25

—
—
—

4.0

8.0

12.5

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 1.2
– 0.25
– 0.62

– 1.8

—
—
—
—

– 1.0
– 0.2
– 0.5
– 1.5

– 1.7

– 0.36

– 0.9
– 3.5

—
—
—
—

– 0.7
– 0.14
– 0.35

– 1.1

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

mAdc

Input Current

I

in

15

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

ÎÎÎ

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

—

—

—

5.0

7.5

—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—

pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

0.25

0.5

1.0

—
—
—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

7.5
15
30

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)

I

T

5.0
10
15

IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.8 µA/kHz) f + IDD/N

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µH (per package), CL in pF , V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATAMC14000UB

4

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise Time

t

TLH

= (3.0 ns/pF) CL + 30 ns

t

TLH

= (1.5 ns/pF) CL + 15 ns

t

TLH

= (1.1 ns/pF) CL + 10 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

TLH

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

180

90
65

360
180
130

ns

Output Fall Time

t

THL

= (1.5 ns/pF) CL + 25 ns

t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

THL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

100

50
40

200
100

80

ns

Propagation Delay Time

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 30 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 22 ns

t

PLH

, t

PHL

= (0.50 ns/pF) CL + 15 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

PLH

,

t

PHL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

115

55
40

230

110

80

ns

*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

V

DD

14

C

L

VSS7

PULSE

GENERATOR

INPUT

OUTPUT

90%

50%

10%

10%

50%

90%

20 ns 20 ns

t

PHL

t

PLH

t

TLH

t

THL

V

OL

V

OH

V

SS

V

DD

INPUT

OUTPUT

Figure 1. Switching Time Test Circuit and Waveforms

Figure 2. Typical Voltage and Current

Transfer Characteristics

Figure 3. Typical Voltage Transfer

Characteristics versus Temperature

16
14

12
10

8.0

6.0

4.0

2.0
0

8.0

6.0

4.0

2.0
0

161412108.06.04.02.00

V

out

, OUTPUT VOLTAGE (Vdc)

I

D

, DRAIN CURRENT (mAdc)

Vin, INPUT VOLTAGE (Vdc)

TA = 25°C

a ONE INPUT ONLY

AND INVERTER
b TWO INPUTS
c THREE INPUTS

ID = 15 Vdc

ID = 10 Vdc

10 Vdc

5.0 Vdc

a

a

b

b

a

b

c

c

c

VDD = 15 Vdc

16
14

12
10

8.0

6.0

4.0

2.0
0

V

out

, OUTPUT VOLTAGE (Vdc)

161412108.06.04.02.00

Vin, INPUT VOLTAGE (Vdc)

b

b

b

a

a TA = + 125°C
b TA = – 55

°

C

10 Vdc

5.0 Vdc

VDD = 15 Vdc

UNUSED INPUTS
CONNECTED TO V

SS

a

a

MOTOROLA CMOS LOGIC DATA

5

MC14000UB

OUTLINE DIMENSIONS

L SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC

J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

C

14 PLD

GF N

K

14 PLJ

M

L

S

B

M

0.25 (0.010) T

S

A

M

0.25 (0.010) T

–T–

SEATING
PLANE

1 7

14 9

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

B

A

F

H G D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01

_ _ _ _

MOTOROLA CMOS LOGIC DATAMC14000UB

6

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

_ _ _ _

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14000UB/D

*MC14000UB/D*

◊