Datasheet MC12429FN Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 5

 Motorola, Inc. 1997

1/97

   

The MC12429 is a general purpose synthesized clock source targeting
applications that require both serial and parallel interfaces. Its internal
VCO will operate over a range of frequencies from 400 to 800MHz. The
differential PECL output can be configured to be the VCO frequency
divided by 2, 4, 8 or 16. With the output configured to divide the VCO
frequency by 2, and with a 16.000MHz external quartz crystal used to
provide the reference frequency, the output frequency can be specified in
1MHz steps. The PLL loop filter is fully integrated so that no external
components are required.

• 25 to 400MHz Differential PECL Outputs

• ±25ps Peak–to–Peak Output Jitter

• Fully Integrated Phase–Locked Loop

• Minimal Frequency Over–Shoot

• Synthesized Architecture

• Serial 3–Wire Interface

• Parallel Interface for Power–Up

• Quartz Crystal Interface

• 28–Lead PLCC Package

• Operates from 3.3V or 5.0V Power Supply

Functional Description

The internal oscillator uses the external quartz crystal as the basis of
its frequency reference. The output of the reference oscillator is divided
by 8 before being sent to the phase detector. With a 16MHz crystal, this
provides a reference frequency of 2MHz. Although this data sheet
illustrates functionality only for a 16MHz crystal, any crystal in the
10–25MHz range can be used.

The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.

The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.

The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (2, 4, 8, or

16). This divider extends performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
in 50Ω to VCC – 2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD

input is held LOW until sometime after power

becomes valid. On the LOW–to–HIGH transition of P_LOAD

, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.

The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.



HIGH FREQUENCY PLL

CLOCK GENERATOR

FN SUFFIX

28–LEAD PLCC PACKAGE

CASE 776–02

MC12429

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

2

1

N[1]

N[0]

M[8]

M[7]

M[6]

M[5]

M[4]XTAL1

NC

NC

PLL–V

CC

S_LOAD

S_DATA

S_CLOCK

4

3

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11109

7

8

6

5

Figure 1. 28–Lead (Top View)

P_LOAD

VCCFOUT FOUT GND VCCTEST GND

M[3]M[2]M[1]M[0]

OE

XTAL2

N[1:0]

0 0
0 1
1 0
1 1

Output Division

2
4
8

16

PIN DESCRIPTIONS

Pin Name Function

Inputs

XTAL1, XTAL2 These pins form an oscillator when connected to an external series–resonant crystal.
S_LOAD

(Int. Pulldown)

This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this
signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.

S_DATA
(Int. Pulldown)

This pin acts as the data input to the serial configuration shift registers.

S_CLOCK
(Int. Pulldown)

This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.

P_LOAD
(Int. Pullup)

This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this
signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD

for proper operation.

M[8:0]
(Int. Pullup)

These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of P_LOAD. M[8]
is the MSB, M[0] is the LSB.

N[1:0]
(Int. Pullup)

These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition of
P_LOAD

.

OE
(Int. Pullup)

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the F

OUT

output.

Outputs

F

OUT

, F

OUT

These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.

TEST The function of this output is determined by the serial configuration bits T[2:0].

Power

V

CC

This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V
(VCC = PLL_VCC). Current drain through VCC ≈ 85mA.

PLL_V

CC

This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is
connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC ≈ 15mA.

GND These pins are the negative supply for the chip and are normally all connected to ground.

MC12429

TIMING SOLUTIONS
BR1333 — Rev 6

3 MOTOROLA

9–BIT

SR

2–BIT

SR

3–BIT SR

DIV 8

Figure 2. MC12429 Block Diagram

16MHz

S_LOAD
P_LOAD

S_DATA

S_CLOCK

XTAL1

XTAL2

OSC

4

5

PHASE

DETECTOR

28

7

9–BIT DIV M

COUNTER

LATCH

VCO

DIV N

(2, 4, 8, 16)

LATCH

400–800

MHz

FOUT
FOUT

+3.3 or 5.0V

25
24

23

V

CC0

LATCH

TEST

20

+3.3 or 5.0V

PLL_V

CC

2MHz
F

REF

01

27

26

01

V

CC1

+3.3 or 5.0V

M[8:0]

9

8

→

16

N[1:0]

2

17, 1821 22, 19

OE

6

PROGRAMMING INTERF ACE

Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:

FOUT = (F

XTAL

÷ 8) x M ÷ N (1)

Where F

XTAL

is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 ≤ M ≤ 400 for a 16MHz input reference.

Assuming that a 16MHz reference frequency is used the

above equation reduces to:

FOUT = 2 x M ÷ N

Substituting the four values for N (2, 4, 8, 16) yields:

FOUT = M, FOUT = M ÷ 2,
FOUT = M ÷ 4 and FOUT = M ÷ 8
for 200 < M < 400

The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 200 – 400MHz, 100 –
200MHz, 50 – 100MHz and 25 – 50MHz respectively. From
these ranges the user will establish the value of N required,
then the value of M can be calculated based on the
appropriate equation above. For example if an output
frequency of 131MHz was desired the following steps would
be taken to identify the appropriate M and N values. 131MHz
falls within the frequency range set by an N value of 4 so N
[1:0] = 01. For N = 4 FOUT = M ÷ 2 and M = 2 x FOUT.
Therefore M = 131 x 2 = 262, so M[8:0] = 100000110.
Following this same procedure a user can generate any
whole frequency desired between 25 and 400MHz. Note that
for N > 2 fractional values of FOUT can be realized. The size
of the programmable frequency steps (and thus the indicator
of the fractional output frequencies acheivable) will be equal
to FXTAL ÷ 8 ÷ N.

For input reference frequencies other than 16MHz the set
of appropriate equations can be deduced from equation 1.
For computer applications another useful frequency base
would be 16.666MHz. From this reference one can generate
a family of output frequencies at multiples of the 33.333MHz
PCI clock. As an example to generate a 133.333MHz clock

MC12429

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

4

from a 16.666MHz reference the following M and N values
would be used:

FOUT = 16.666 ÷ 8 x M ÷ N = 2.083333 x M ÷ N

Let N = 4, M = 133.3333 ÷ 2.083333 x 4 = 256

The value for M falls within the constraints set for PLL
stability, therefore N[1:0] = 01 and M[8:0} = 10000000. If the
value for M fell outside of the valid range a different N value
would be selected to try to move M in the appropriate
direction.

The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD

signal such that a LOW to HIGH transition
will latch the information present on the M[8:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD

signal is
LOW the input latches will be transparent and any changes
on the M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port the S_CLOCK signal samples the
information on the S_DA TA line and loads it into a 14 bit shift
register. Note that the P_LOAD

signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and
the M register with the final eight bits of the data streeam on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin
after the shift register is fully loaded will transfer the divide
values into the counters. The HIGH to LOW transition on the
S_LOAD input will latch the new divide values into the
counters. Figure 3 illustrates the timing diagram for both a
parallel and a serial load of the MC12429 synthesizer.

M[8:0] and N[1:0] are normally specified once at power–up
through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine–tune the clock as the ability to control the serial interface
becomes available. To minimize transients in the frequency
domain, the output should be varied in the smallest step size
possible. The bandwidth of the PLL is such that frequency
stepping in 1MHz steps at the maximum S_CLOCK
frequency or less will cause smooth, controlled slewing of the
output frequency.

The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the CMOS output may not be able to
toggle fast enough for some of the higher output frequencies.
The T2, T1 and T0 control bits are preset to ‘000’ when
P_LOAD

is LOW so that the PECL FOUT outputs are as
jitter–free as possible. Any active signal on the TEST output
pin will have detrimental affects on the jitter of the PECL
output pair. In normal operations, jitter specifications are only
guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin.

Most of the signals available on the TEST output pin are
useful only for performance verification of the MC12429
itself. However the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to 110
the MC12429 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The
N divider drives the FOUT differential pair and the M counter
drives the TEST output pin. In this mode the S_CLOCK input
could be used for low speed board level functional test or
debug. Bypassing the PLL and driving FOUT directly gives
the user more control on the test clocks sent through the
clock tree. Figure 4 shows the functional setup of the PLL
bypass mode. Because the S_CLOCK is a CMOS level the
input frequency is limited to 250MHz or less. This means the
fastest the FOUT pin can be toggled via the S_CLOCK is
125MHz as the minimum divide ratio of the N counter is 2.
Note that the M counter output on the TEST output will not be
a 50% duty cycle due to the way the divider is implemented.

T2 T1 T0 TEST (Pin 20)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT/4

Figure 3. Timing Diagram

S_CLOCK

S_DATA

S_LOAD

M[8:0]

N[1:0]

P_LOAD

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1

M0

M, N

First

Bit

Last

Bit

MC12429

TIMING SOLUTIONS
BR1333 — Rev 6

5 MOTOROLA

Figure 4. Serial Test Clock Block Diagram

FDIV4
MCNT

LOW
FOUT
MCNT

FREF

HIGH

TEST

MUX

7

0

TEST

FOUT

(VIA ENABLE GATE)

N DIVIDE

(2, 4, 8, 16)

0
1

PLL 12429

LATCH

Reset

PLOADB

M COUNTER

SLOAD

T0
T1
T2

VCO_CLK

SHIFT

REG

14–BIT

DECODE

SDATA

SCLOCK

MCNT

FREF

SEL_CLK

•

T2=T1=1, T0=0: Test Mode

•

SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin

PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)

Symbol Characteristic Min Typ Max Unit Condition

V

IH

Input HIGH Voltage 2.0 V VCC = 3.3 to 5.0V

V

IL

Input LOW Voltage 0.8 V VCC = 3.3 to 5.0V

I

IN

Input Current 1.0 mA

V

OH

Output HIGH Voltage TEST 2.5 V IOH = –0.8mA

V

OL

Output LOW Voltage TEST 0.4 V IOL = 0.8mA

V

OH

Output HIGH Voltage FOUT

FOUT

2.17 2.50 V V

CC0

= 3.3V (Notes 1., 2.)

V

OL

Output LOW Voltage FOUT

FOUT

1.41 1.76 V V

CC0

= 3.3V (Notes 1., 2.)

I

CC

Power Supply Current V

CC

PLL_V

CC

85
15

100

20

mA

1. Output levels will vary 1:1 with V

CC0

variation.

2. 50Ω to VCC – 2.0V pulldown.

MC12429

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

6

AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)

Symbol Characteristic Min Max Unit Condition

F

MAXI

Maximum Input Frequency S_CLOCK

Xtal Oscillator 10

10
20

MHz Note 3.

F

MAXO

Maximum Output Frequency VCO (Internal)

FOUT

400

25

800
400

MHz Note 4.

t

LOCK

Maximum PLL Lock Time 10 ms

t

jitter

Cycle–to–Cycle Jitter (Peak–to–Peak) ±25 ps Note 4.,

See Applications Section

t

s

Setup Time S_DATA to S_CLOCK

S_CLOCK to S_LOAD

M, N to P_LOAD

20
20
20

ns

t

h

Hold Time S_DATA to S_CLOCK

M, N to P_LOAD

20
20

ns

tpw

MIN

Minimum Pulse Width S_LOAD

P_LOAD

50
50

ns Note 4.

tr, t

f

Output Rise/Fall FOUT 300 800 ps 20%–80%, Note 4.

3. 10MHz is the maximum frequency to load the feedback devide registers. S_CLOCK can be switched at higher frequencies when used as a
test clock in TEST_MODE 6.

4. 50Ω to VCC – 2.0V pulldown.

APPLICATIONS INFORMATION

Using the On–Board Crystal Oscillator

The MC12429 features a fully integrated on–board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is
advised to mount the crystal as close to the MC12429 as
possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the xtal terminals loading variation
introduced by crystals from different vendors could be a
potential issue. For crystals with a higher shunt capacitance it
may be required to place a resistance across the terminals to
suppress the third harmonic. Although typically not required it
is a good idea to layout the PCB with the provision of adding
this external resistor. The resistor value will typically be
between 500 and 1KΩ.

The oscillator circuit is a series resonant circuit and thus
for optimum performance a series resonant crystal should be
used. Unfortunately most crystals are characterized in a
parallel resonant mode. Fortunately there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are

characterized. As a result a parallel resonant crystal can be
used with the MC12429 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified, a few hundred ppm
translates to kHz inaccuracies. In a general computer
application this level of inaccuracy is immaterial. Table 1
below specifies the performance requirements of the crystals
to be used with the MC12429.

Table 1. Crystal Specifications

Parameter Value

Crystal Cut Fundamental AT Cut
Resonance Series Resonance*
Frequency Tolerance ±75ppm at 25°C
Frequency/Temperature Stability ±150pm 0 to 70°C
Operating Range 0 to 70°C
Shunt Capacitance 5–7pF
Equivalent Series Resistance (ESR) 50 to 80Ω
Correlation Drive Level 100µW
Aging 5ppm/Yr (First 3 Y ears)

* See accompanying text for series versus parallel resonant

discussion.

MC12429

TIMING SOLUTIONS
BR1333 — Rev 6

7 MOTOROLA

Power Supply Filtering

The MC12429 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MC12429 provides separate
power supplies for the digital ciruitry (VCC) and the internal
PLL (PLL_VCC) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the PLL_VCC pin for the MC12429.

Figure 5 illustrates a typical power supply filter scheme.
The MC12429 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the
PLL_VCC pin of the MC12429. From the data sheet the
I

PLL_VCC

current (the current sourced through the PLL_VCC
pin) is typically 15mA (20mA maximum), assuming that a
minimum of 3.0V must be maintained on the PLL_VCC pin
very little DC voltage drop can be tolerated when a 3.3V V

CC

supply is used. The resistor shown in Figure 5 must have a
resistance of 10–15Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20KHz. As the noise frequency crosses the
series resonant point of an individual capacitor it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.

Figure 5. Power Supply Filter

PLL_VCC

VCC

MC12429

0.01µF

22

µ

F

L=1000

µ

H

R=15

Ω

0.01µF

3.3V or

5.0V

RS=10–15

Ω

3.3V or

5.0V

A higher level of attenuation can be acheived by replacing
the resistor with an appropriate valued inductor. Figure 5
shows a 1000µH choke, this value choke will show a
significant impedance at 10KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin a low DC resistance

inductor is required (less than 15Ω). Generally the
resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering.

The MC12429 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representaive board layout for the
MC12429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 6 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors with
good PCB layout techniques will produce effective capacitor
resonances at frequencies adequate to supply the
instantaneous switching current for the 12429 outputs. It is
imperative that low inductance chip capacitors are used; it is
equally important that the board layout does not introduce
back all of the inductance saved by using the leadless
capacitors. Thin interconnect traces between the capacitor
and the power plane should be avoided and multiple large
vias should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.

Figure 6. PCB Board Layout for MC12429

C2

1

C3

R1

Xtal

C1 C1

R1 = 10–15

Ω

C1 = 0.01µF
C2 = 22

µ

F

C3 = 0.1

µ

F

= V

CC

= GND
= Via

Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the device.
Special attention should be paid to the layout of the crystal to
ensure a stable, jitter free interface between the crystal and
the on–board oscillator. Note the provisions for placing a
resistor across the crystal oscillator terminals as discussed in
the crystal oscillator section of this data sheet.

Although the MC12429 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may

MC12429

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

8

be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.

Jitter Performance of the MC12429

The MC12429 exhibits long term and cycle–to–cycle jitter
which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility one gets with a
synthesizer over a fixed frequency oscillator.

Figure 7. RMS PLL Jitter versus VCO Frequency

0

5

10

15

20

25

400 500 600 700 800

N=2
N=4
N=8

VCO Frequency (MHz)

RMS Jitter (ps)

N=16

Figure 7 illustrates the RMS jitter performance of the
MC12429 across its specified VCO frequency range. Note
that the jitter is a function of both the output frequency as well
as the VCO frequency, however the VCO frequency shows a
much stronger dependence. The data presented has not
been compensated for trigger jitter, this fact provides a
measure of guardband to the reported data. In addition the
data represents long term period jitter, the cycle–to–cycle
jitter could not be measured to the level of accuracy required
with available test equipment but certainly will be smaller
than the long term period jitter.

The most commonly specified jitter parameter is
cycle–to–cycle jitter. Unfortunately with today’s high
performance measurement equipment there is no way to
measure this parameter for jitter performance in the class

demonstrated by the MC12429. As a result different methods
are used which approximate cycle–to–cycle jitter. The typical
method of measuring the jitter is to accumulate a large
number of cycles, create a histogram of the edge placements
and record peak–to–peak as well as standard deviations of
the jitter. Care must be taken that the measured edge is the
edge immediately following the trigger edge. The
oscilloscope cannot collect adjacent pulses, rather it collects
pulses from a very large sample of pulses. It is safe to
assume that collecting pulse information in this mode will
produce period jitter values somewhat larger than if
consecutive cycles (cycle–to–cycle jitter) were measured. All
of the jitter data reported on the MC12429 was collected in
this manner.

Figure 8 shows the jitter as a function of the output
frequency. For the 12429 this information is probably of more
importance. The flat line represents an RMS jitter value that
corresponds to an 8 sigma ±25ps peak–to–peak long term
period jitter. The graph shows that for output frequencies
from 87.5 to 400MHz the jitter falls within the ±25ps
peak–to–peak specification. The general trend is that as the
output frequency is decreased the output edge jitter will
increase.

Figure 8. RMS Jitter versus Output Frequency

0

5

10

15

20

25

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Output Frequency (MHz)

RMS Jitter (ps)

6.25ps Reference

The jitter data presented should provide users with
enough information to determine the effect on their overall
timing budget. The jitter performance meets the needs of
most system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.

MC12429

TIMING SOLUTIONS
BR1333 — Rev 6

9 MOTOROLA

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776–02

ISSUE D

NOTES:

1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

–N–

–M–

–L–

V

W

D

D

Y BRK

28 1

VIEW S

S

L–M

S

0.010 (0.250) N

S

T

S

L–M

M

0.007 (0.180) N

S

T

0.004 (0.100)

G1

G

J

C

Z

R

E

A

SEATING
PLANE

S

L–M

M

0.007 (0.180) N

S

T

–T–

B

S

L–M

S

0.010 (0.250) N

S

T

S

L–M

M

0.007 (0.180) N

S

T

U

S

L–M

M

0.007 (0.180) N

S

T

Z

G1X

VIEW D–D

S

L–M

M

0.007 (0.180) N

S

T

K1

VIEW S

H

K

F

S

L–M

M

0.007 (0.180) N

S

T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C 0.165 0.180 4.20 4.57

E 0.090 0.110 2.29 2.79

F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81

J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58

V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21

X 0.042 0.056 1.07 1.42

Y ––– 0.020 ––– 0.50

Z 2 10 2 10

G1 0.410 0.430 10.42 10.92
K1 0.040 ––– 1.02 –––

____

MC12429

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

10

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
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MC12429/D

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