Datasheet MC12206DT, MC12206D Datasheet (Motorola)

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Page 1



SEMICONDUCTOR TECHNICAL DATA

REV 3

 Motorola, Inc. 1997

1/97

    

The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse–swallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications.

Motorola’s advanced Bipolar MOSAIC V technology is utilized for low power operation at a minimum supply voltage of 2.7V. The device is designed for operation over 2.7 to 5.5V supply range for input frequencies up to 2.0GHz with a typical current drain of 7.4mA. The low power consumption makes the MC12206 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 64/65 or 128/129 divide ratio.

For additional applications information, two

InterActiveApNote



documents containing software (based on a Microsoft Excel spreadsheet) and an Application Note are available. Please order DK305/D and DK306/D from the Motorola Literature Distribution Center.

• Low Power Supply Current of 6.7mA Typical for I

and 0.7mA Typical

for I

• Supply Voltage of 2.7 to 5.5V

• Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or

128/129

• On–Chip Reference Oscillator/Buffer

• Programmable Reference Divider Consisting of a Binary 14–Bit

Programmable Reference Counter

• Programmable Divider Consisting of a Binary 7–Bit Swallow Counter

and an 11–Bit Programmable Counter

• Phase/Frequency Detector With Phase Conversion Function

• Balanced Charge Pump Outputs

• Dual Internal Charge Pumps for Bypassing the First Stage of the Loop

Filter to Decrease Lock Time

• Outputs for External Charge Pump

• Operating Temperature Range of –40°C to +85°C

• Space Efficient Plastic Surface Mount SOIC or TSSOP Packages

MAXIMUM RATINGS*

Symbol

Parameter Value Unit

Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package) –0.5 to +6.0 VDC

Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package) VCC to +6.0 VDC

stg

Storage Temperature Range –65 to +150 °C

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

MOSAIC V , Mfax and

InterActiveApNote

are trademarks of Motorola, Inc.



D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

MECL PLL COMPONENTS

Serial Input PLL

Frequency Synthesizer

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–03

Page 2

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

OSCin

OSCout

OUT

BISW

Pinout: 16–Lead Package (Top View)

GND

DATA

CLK

OSCin

OSCout

OUT

Pinout: 20–Lead Package (Top View)

BISW

GND

DATA

CLK

PIN NAMES

Pin I/O Function

16–Lead Pkg

Pin No.

20–Lead Pkg

Pin No.

OSCin I Oscillator input. A crystal is connected between OSCin and OSCout. An external

source can be AC coupled into this input

1 1

OSCout O Oscillator output. Pin should be left open if external source is used 2 3 V

— Power supply for charge pumps (VP should be greater than or equal to VCC) V

provides power to the Do, BISW and φP outputs

3 4

— Power supply voltage input. Bypass capacitors should be placed as close as

possible to this pin and be connected directly to the ground plane.

4 5

Do O Internal charge pump output. Do remains on at all times 5 6 GND — Ground 6 7 LD O Lock detect, phase comparator output 7 8 f

I Prescaler input. The VCO signal is AC–coupled into this pin 8 10 CLK I Clock input. Rising edge of the clock shifts data into the shift registers 9 11 DATA I Binary serial data input 10 13 LE I Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data

stored in the shift register is transferred into the appropriate latch (depending on the level of control bit). Also, when LE is HIGH or OPEN, the output of the second internal charge pump is connected to the BISW pin

11 14

FC I Phase control select (with internal pull up resistor). When FC is LOW, the

characteristics of the phase comparator and charge pump are reversed. FC also selects fp or fr on the f

OUT

12 15

BISW O Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the

output of the second charge pump is connected to the BISW pin. When LE is LOW, BISW is high impedance

13 16

OUT

O Phase comparator input signal. When FC is HIGH, f

OUT

=fr, programmable

reference divider output; when FC is LOW, f

OUT

=fp, programmable divider output

14 17

φP O Output for external charge pump. Standard CMOS output level 15 18 φR O Output for external charge pump. Standard CMOS output level 16 20

NC — No connect — 2, 9, 12, 19

Page 3

MC12206

HIPERCOMM BR1334 — Rev 4

3 MOTOROLA

Figure 1. MC12206 Block Diagram

15–BIT SHIFT REGISTER

15–BIT LATCH

14–BIT REFERENCE COUNTER

CRYST AL

OSCILLAT OR

OSCin

OSCout

PHASE/FREQUENCY

DETECTOR

CHARGE

PUMP 1

CHARGE

PUMP 2

BISW

PROGRAMMABLE REFERENCE DIVIDER

18–BIT SHIFT REGISTER

7–BIT

LATCH

11–BIT LATCH

DATA

CLK

PROGRAMMABLE DIVIDER

7–BIT

SWALLOW

A–COUNTER

11–BIT

PROGRAMMABLE

N–COUNTER

CONTROL LOGIC

PRESCALER

64/65 or 128/129

DIVIDER

OUTPUT MUX

OUT

14 1

7 11

CONTROL

BIT

DATA

Page 4

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

DATA ENTRY FORMAT

The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable pin is HIGH or OPEN.

Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider

“L” = data is transferred into 18–bit latch of programmable divider

WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect the VCO.

PROGRAMMABLE REFERENCE DIVIDER

16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to

16383) and the prescaler divide ratio (SW=0 for ÷128/129, SW=1 for ÷64/65). An R divide ratio less than 8 is prohibited. For Control bit (C) = HIGH:

R 3

R 4

R 5

R 6

R 7

R 9

SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE

REFERENCE COUNTER (R–COUNTER)

MSB

SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)

LSB

CONTROL BIT (LAST BIT)

DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER

Divide

Ratio R

R 9

R 8

R 7

R 6

R 5

R 3

R 2

1 8 0 0 0 0 0 0 0 0 0 0 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 1 0 0 1

• • • • • • • • • • • • • • •

16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PRESCALER SELECT BIT

Prescaler Divide Ratio P SW

128/129 0

64/65 1

Page 5

MC12206

HIPERCOMM BR1334 — Rev 4

5 MOTOROLA

PROGRAMMABLE DIVIDER

19–bit serial data format for the programmable divider is shown below. If the control bit is LOW , data is transferred from the 18–bit shift register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter divide ratio (16 to 2047). An N–counter divide ratio less than 16 is prohibited.

For Control bit (C) = LOW:

SETTING BITS FOR

DIVIDE RATIO OF

SWALLOW A–COUNTER

A 2

A 3

A 4

A 5

A 6

A 7

N 8

N 9

LSB

MSB (FIRST BIT) CONTROL BIT (LAST BIT)

SETTING BITS FOR

DIVIDE RATIO OF

PROGRAMMABLE N–COUNTER

DIVIDE RATIO OF PROGRAMMABLE N–COUNTER DIVIDE RATIO OF SWALLOW A–COUNTER

Divide

Ratio NN18N17N16N15N14N13N12N11N10N9N8

Divide

Ratio AA7A6A5A4A3A2A1 16 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1

• • • • • • • • • • • • • • • • • • • •

2047 1 1 1 1 1 1 1 1 1 1 1 127 1 1 1 1 1 1 1

DIVIDE RATIO SETTING

fvco = [(P•N)+A]•fosc ÷ R with A<N

fvco: Output frequency of external voltage controlled oscillator (VCO) N: Preset divide ratio of binary 11–bit programmable counter (16 to 2047) A: Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N) fosc: Output frequency of the external frequency oscillator R: Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383) P: Preset mode of dual modulus prescaler (64 or 128)

Figure 2. Serial Data Input Timing

N18:MSB N17

(SW:MSB) (R14)

N8 A7

(R7) (R6)

A1 C = CONTROL BIT (LAST BIT)

(R1) (C = CONTROL BIT (LAST BIT))

ts(D) th(D) t

ts(C→LE)

DATA

CLK

NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.

ts(D) = Setup Time DA TA to CLK ts(D)

≥

10ns

th(D) = Hold Time DA TA to CLK th(D)

≥

20ns

tCW = CLK Pulse Width tCW

≥

30ns

tEW = LE Pulse Width tEW ≥20ns

ts(C

→

LE) = Setup Time CLK to LE ts(C→LE) ≥30ns

Page 6

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

PHASE CHARACTERISTICS/VCO CHARACTERISTICS

The phase comparator in the MC12206 is a high speed digital phase frequency detector circuit. The circuit determines the “lead” or “lag” phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input. Since these edges occur only once per cycle, the detector has a range of ±2π radians. The phase comparator outputs are standard CMOS rail–to–rail levels (VP to GND for φP and VCC to GND for φR), designed for up to 20MHz operation into a 15pF load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics.

The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are controlled by the FC pin. The polarity of the phase comparator outputs, φR and φP, as well as the charge pump output Do can be reversed by switching the FC pin.

Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms

Do (FC = H)

R (FC = H)

P (FC = H)

Do (FC = L)

R (FC = L)

P (FC = L)

Source

Sink

Source

Sink

NOTES: Do and BISW are current outputs.

Phase difference detection range: –2

to +2

Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.

BISW (LE = H or Open)

Internal Charge Pump Gain

[

source

)

sink

4mA

Page 7

MC12206

HIPERCOMM BR1334 — Rev 4

7 MOTOROLA

For FC = HIGH: fr lags fp in phase OR fp>fr in frequency

When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φR indicates to the VCO to decrease in frequency to bring the loop into lock.

fr leads fp in phase OR fp<fr in frequency

When the phase of fr leads that of fp or the frequency of fp is less than fr, the φR output will remain in a LOW state while the φP output pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φP indicates to the VCO to increase in frequency to bring the loop to lock.

fr = fp in phase and frequency

When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will maintain the loop in its locked state.

When FC = LOW, the operation of the phase comparator is reversed from the above explanation.

For FC = LOW: fr lags fp in phase OR fp>fr in frequency

When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φP indicates to the VCO to increase in frequency to bring the loop into lock.

fr leads fp in phase OR fp<fr in frequency

When the phase of fr leads that of fp or the frequency of fp is less than fr, the φP output will remain in a HIGH state while the φR output pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φR indicates to the VCO to decrease in frequency to bring the loop to lock.

fr = fp in phase and frequency

The FC pin controls not only the phase characteristics, but also controls the f

OUT

test pin. The FC pin permits the user to monitor

either of the phase comparator input signals, fr or fp, at the f

OUT

output providing a test mode where the programming of the

dividers and the output of the counters can be checked. When FC is HIGH, f

OUT

= fr, the programmable reference divider output.

When FC is LOW, f

OUT

= fp, the programmable divider output. Hence, If VCO characteristics are like (1), FC should be set HIGH or OPEN. f

OUT

= fr

If VCO characteristics are like (2), FC should be set LOW. f

OUT

= fp

Figure 4. VCO Characteristics

VCO INPUT VOLTAGE

VCO OUTPUT FREQUENCY

( 1 )

( 2 )

FC = HIGH or OPEN FC = LOW

Do φR φP f

OUT

Do φR φP f

OUT

fp < fr H L L fr L H H fp fp > fr L H H fr H L L fp fp = fr Z L H fr Z L H fp

NOTES:Z = High impedance

When LE is HIGH or Open, BISW has the same characteristics as Do.

Figure 5. Phase Comparator, Internal Charge Pump, and

OUT

Characteristics

Page 8

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

Figure 6. Detailed Phase Comparator Block Diagram

PHASE

FREQUENCY

DETECTOR

DOWN

PHASE COMPARATOR

CHARGE

PUMP 1

CHARGE

PUMP 2

BISW

LOCK DETECT

The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally HIGH. LD is designed to be the logical NORing of the phase frequency detector’s outputs UP and DOWN. See Figure 6. In typical applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.

OSCILLATOR INPUT

For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be between 500 and 2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the internal voltage reference.

The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum of 30 pF each including parasitic and stray capacitance).

DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)

Due to the pure Bipolar nature of the MC12206 design, the “analog switch” function is implemented with dual internal charge pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time.

When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin, and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is LOW, BISW is in a high impedance state and Do output is active.

Figure 7. “Analog Switch” Block Diagram

CHARGE

PUMP 1

CHARGE

PUMP 2

BISW

LPF–1 LPF–2 VCO

Page 9

MC12206

HIPERCOMM BR1334 — Rev 4

9 MOTOROLA

ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5V; TA = –40 to +85°C)

Symbol Parameter Min Typ Max Unit Condition

Supply Current for V

6.7 10.5 mA Note 1

8.1 12.5 Note 2

Supply Current for V

0.7 1.1 mA Note 3

0.8 1.3 Note 4

Operating Frequency fINmax

fINmin

2000

500

MHz Note 5

OSC

Operating Frequency (OSCin) 12 20 MHz Crystal Mode

40 MHz External Reference Mode

Input Sensitivity f

200 1000 mV

P–P

OSC

OSCin 500 2200 mV

P–P

Input HIGH Voltage CLK, DATA, LE, FC 0.7V

Input LOW Voltage CLK, DATA, LE, FC 0.3V

V VCC = 5.5V

Input HIGH Current (DATA and CLK) 1.0 2.0 µA VCC = 5.5V

Input LOW Current (DATA and CLK) –10 –5.0 µA VCC = 5.5V

OSC

Input Current (OSCin) 130

–310

µA OSCin = V

OSCin = VCC – 2.2V

Input HIGH Current (LE and FC) 1.0 2.0 µA

Input LOW Current (LE and FC) –75 –60 µA

Source

Charge Pump Output Current –2.6 –2.0 –1.4 mA VDo = VP/2; VP = 2.7V

Sink

Do and BISW +1.4 +2.0 +2.6 V

BISW

= VP/2; VP = 2.7V

Hi–Z

–15 +15 nA 0.5 < VDO < VP – 0.5

0.5 < V

BISW

< VP – 0.5

Output HIGH Voltage (LD, φR, φP, f

OUT

)

4.4 V VCC = 5.0V

2.4 V VCC = 3.0V

Output LOW Voltage (LD, φR, φP, f

OUT

)

0.4 V VCC = 5.0V

0.4 V VCC = 3.0V

Output HIGH Current (LD, φR, φP, f

OUT

)

–1.0 mA

Output LOW Current (LD, φR, φP, f

OUT

)

1.0 mA

1. VCC = 3.3V, all outputs open. 4. VP = 6.0V, all outputs open.

2. VCC = 5.5V, all outputs open. 5. AC coupling, FIN measured with a 1000pF capacitor.

3. VP = 3.3V, all outputs open. 6. Source current flows out of the pin and sink current flows into the pin.

Figure 8. Typical External Charge Pump Circuit

EXTERNAL CHARGE PUMP OUTPUT

10k

Ω

10k

Ω

12k

Ω

12k

Ω

Figure 9. Typical Lock Detect Circuit

LOCK DETECT OUTPUT

100k

Ω

10k

Ω

33k

Ω

0.01µF

Page 10

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

OSCout

Figure 10. Typical Applications Example (16–Pin Package)

47k

Ω

47k

Ω

EXTERNAL CHARGE PUMP (SEE FIGURE 8)

LOW PASS

FILTER

(SEE FIGURE 11)

VCO

FOUT

BISW

DATA

CLK

GND

OSCin

1000pF

LOCK

DETECT

LOCK DETECT

CIRCUIT

(SEE FIGURE 9)

0.1µF

CHARGE PUMP SELECTION

(INTERNAL OR EXTERNAL)

C1, C2: Dependent on Crystal Oscillator

MC12206

100pF

Figure 11. Typical Loop Filter

Do OR EXTERNAL

CHARGE PUMP

VCO

FROM CONTROLLER

BISW

Page 11

MC12206

HIPERCOMM BR1334 — Rev 4

11 MOTOROLA

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

0.25 (0.010) T B A

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A B C D F G J K M P R

9.80

3.80

1.35

0.35

0.40

0.19

0.10 0

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25 7

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004 0

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

DIMAMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015

J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

NOTES:

12 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 13 CONTROLLING DIMENSION: MILLIMETER. 14 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE. 15 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE. 16 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION. 17 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 18 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

110

1120

PIN 1 IDENT

–T–

0.100 (0.004)

SECTION N–N

JJ1

–W–

SEATING PLANE

–V–

–U–

0.10 (0.004) V

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252 ––– –––

U0.15 (0.006) T

Page 12

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 T anners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, T ai Po Industrial Estate, Tai Po, N.T ., Hong Kong.

MC12206/D

*MC12206/D*

◊

CODELINE TO BE PLACED HERE

Datasheet MC12206DT, MC12206D Datasheet (Motorola)

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Frequently Asked Questions

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